MEMORY READ CIRCUITRY
First Claim
1. A circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit comprising:
- a) a precharge input;
b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;
c) a delay element, the input of the delay element coupled to the precharge input; and
d) a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
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Accused Products
Abstract
A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
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Citations
22 Claims
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1. A circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit comprising:
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a) a precharge input;
b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;
c) a delay element, the input of the delay element coupled to the precharge input; and
d) a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A read circuit on a semiconductor comprising:
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a) a precharge input;
b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to a local bitline;
c) a first delay element, the input of the first delay element coupled to the precharge input;
d) a second delay element, the input of the second delay element coupled to the output of the first delay element;
e) a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline;
f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source;
g) a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground;
h) a fifth switch, the gate of the fifth switch coupled to the bitline, the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and
i) a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer system comprising:
a) a central processing unit, the central processing unit including a circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit including;
1) a precharge input;
2) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;
3) a delay element, the input of the delay element coupled to the precharge input; and
4) a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
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22. A Dynamic Random Access Device (DRAM), the DRAM including a circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit including:
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a) a precharge input;
b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;
c) a delay element, the input of the delay element coupled to the precharge input; and
d) a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
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Specification