Device and method for detecting a reliability of integrated semiconductor components at high temperatures

• US 20030020131A1
• Filed: 07/23/2002
• Published: 01/30/2003
• Est. Priority Date: 07/23/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Martin, Andreas, Hagen, Jochen Von, Smeets, David, Fazekas, Josef, Asam, Wilhelm
• Granted Patent: US 6,787,799 B2
• Time in Patent Office: Days
• US Class Current: 257/467
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/3173 Marginal testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications

Abstract

The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for receiving an integrated semiconductor component that will be examined, a heating element, and a temperature sensor. The temperature sensor has at least a portion of a parasitic functional element of the semiconductor component. As a result, reliability tests can be carried out in a particularly accurate and space-saving manner.

Claims

1. In combination with an integrated semiconductor component having a parasitic functional element, a device for detecting a reliability of the integrated semiconductor component, the device comprising:

a carrier substrate for receiving the integrated semiconductor component;

a heating element for heating the semiconductor component; and

a temperature sensor for detecting a temperature of the semiconductor component;

said temperature sensor including at least a portion of said parasitic functional element of the semiconductor component.

2. The combination according to claim 1, wherein:

said parasitic functional element is a parasitic pn junction.

3. The combination according to claim 1, wherein:

said parasitic functional element is a parasitic bipolar transistor.

4. The combination according to claim 1, wherein:

said parasitic functional element is a diode selected from a group consisting of a parasitic Schottky diode and a MOS diode.

5. The combination according to claim 1, wherein:

the semiconductor component includes a component selected from a group consisting of a resistor, a capacitance, an inductance, a diode, a field-effect transistor, a bipolar transistor and a thyristor.

6. The combination according to claim 1, wherein:

said heating element is buried in direct proximity to the semiconductor component in said carrier substrate.

7. The combination according to claim 1, comprising:

an additional functional element for completing said parasitic partial functional element.

8. The combination according to claim 7, wherein:

said additional functional element includes a component selected from a group consisting of at least one doping region and a connection.

9. The combination according to claim 1, wherein:

the semiconductor component has a region that is of relevance during testing, and said parasitic functional element lies in direct proximity to said region.

10. A method for detecting a reliability of an integrated semiconductor component, which comprises:

using a temperature sensor including at least a portion of a parasitic functional element of the semiconductor component to perform a measurement mode for measuring a temperature that is caused by a heating element and that is actually present at the semiconductor component;

performing a stress mode for stressing the semiconductor component at least in a manner dependent on a temperature of the heating element; and

evaluating a failure instant of the semiconductor component at least in a manner dependent on the temperature that is caused by the heating element.

11. The method according to claim 10, which comprises:

during the stressing, altering an electrical parameter selected from a group consisting of a stress current density and a stress voltage in the semiconductor component; and

during the evaluating, taking the electrical parameter into account.

12. The method according to claim 10, which comprises:

during the measurement mode, impressing a very small measurement current on the temperature sensor.

13. The method according to claim 10, which comprises:

during the measurement mode, deriving a temperature that is actually present at the semiconductor component from a characteristic curve selected from a group consisting of an I/V characteristic curve of the parasitic functional element and a C/V characteristic curve of the parasitic functional element.

14. The method according to claim 10, which comprises:

performing the measurement mode and the stress mode separately from each other with respect to time.

15. The method according to claim 10, which comprises:

during the measurement mode, calibrating the heating element; and

during the stress mode, stressing the semiconductor component in a manner dependent on the heating element that has been calibrated.

16. The method according to claim 10, which comprises:

simultaneously performing the measurement mode and the stress mode.