Array substrate for in-plane switching liquid crystal display device

• US 20030020861A1
• Filed: 07/25/2002
• Published: 01/30/2003
• Est. Priority Date: 07/27/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Yoo, Jang-Jin
• Granted Patent: US 6,885,424 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Abstract

An array substrate for an in-plane switching liquid crystal display device includes a substrate, a gate line and a data line on the substrate, wherein the gate line and the data line cross each other to define a pixel region. A thin film transistor is electrically connected to the gate line and the data line. A common line is parallel to the gate line. A plurality of common electrodes perpendicularly extend from the common line. A plurality of pixel electrodes alternate with the plurality of common electrodes. An overcoat layer is formed over the plurality of common electrodes and the plurality of pixel electrodes, the overcoat layer having a plurality of holes.

Claims

1. An array substrate for an in-plane switching liquid crystal display device, comprising:

a substrate;

a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region;

a thin film transistor being electrically connected to the gate line and the data line;

a common line parallel to the gate line;

a plurality of common electrodes perpendicularly extended from the common line;

a plurality of pixel electrodes alternating with the plurality of common electrodes; and

an overcoat layer over the plurality of common and pixel electrodes, the overcoat layer having a plurality of holes.

2. The array substrate according to claim 1, wherein the plurality of holes are over the plurality of common and pixel electrodes.

3. The array substrate according to claim 2, wherein the plurality of holes over the plurality of common electrodes have a first line and the plurality of holes over the plurality of pixel electrodes have a second line, the first line and the second line spaced apart from each other.

4. The array substrate according to claim 3, further comprising a liquid crystal layer over the overcoat layer, the overcoat layer having a smaller dielectric constant than the liquid crystal layer.

5. The array substrate according to claim 2, wherein each hole has a shape of one of a circle, a triangle, a quadrangle, and a hexagon.

6. The array substrate according to claim 1, wherein the plurality of holes are formed between the plurality of common and pixel electrodes.

7. The array substrate according to claim 6, wherein the plurality of holes have a length along a first direction and a width, the first direction being inclined with respect to the plurality of common and pixel electrodes.

8. The array substrate according to claim 7, wherein the plurality of holes are substantially symmetric with respect to the plurality of common and pixel electrodes.

9. The array substrate according to claim 1, further comprising a liquid crystal layer over the overcoat layer, the liquid crystal layer having one of positive dielectric anisotropy and negative dielectric anisotropy.

10. The array substrate according to claim 1, wherein the overcoat layer is made of one of benzocyclobutene and acrylic resin.

11. An array substrate for an in-plane switching liquid crystal display device, comprising:

a substrate;

a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region;

a thin film transistor being electrically connected to the gate line and the data line;

a common line parallel to the gate line;

a plurality of common electrodes parallel to the common line, the plurality of common electrodes being electrically connected to the common line;

a plurality of pixel electrodes alternating with the plurality of common electrodes; and

an overcoat layer over the plurality of common and pixel electrodes, the overcoat layer having a plurality of holes.

12. The array substrate according to claim 11, wherein the plurality of holes are over the plurality of common and pixel electrodes.

13. The array substrate according to claim 12, wherein the plurality of holes over the plurality of common electrodes have a first line and the plurality of holes over the plurality of pixel electrodes have a second line, the first line and the second line spaced apart from each other.

14. The array substrate according to claim 13, further comprising a liquid crystal layer over the overcoat layer, the overcoat layer having a smaller dielectric constant than the liquid crystal layer.

15. The array substrate according to claim 12, wherein each hole is a shape of one of a circle, a triangle, a quadrangle, and a hexagon.

16. The array substrate according to claim 11, wherein the plurality of holes are formed between the plurality of common and pixel electrodes.

17. The array substrate according to claim 16, wherein the plurality of holes have a length along a first direction and a width, the first direction being inclined with respect to the plurality of common and pixel electrodes.

18. The array substrate according to claim 17, wherein the plurality of holes are substantially symmetric with respect to the plurality of common and pixel electrodes.

19. The array substrate according to claim 11, further comprising a liquid crystal layer over the overcoat layer, the liquid crystal layer having one of positive dielectric anisotropy and negative dielectric anisotropy.

20. The array substrate according to claim 11, wherein the overcoat layer is made of one of benzocyclobutene and acrylic resin.