Integrated dynamic memory and operating method
First Claim
1. An integrated dynamic memory, comprising:
- a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells, said regular memory cells, said first test cells and said second test cells being for storing a charge corresponding to an information bit;
a control unit for refreshing charge contents of said regular memory cells with a first refresh time;
a control unit for refreshing charge contents of said first test cells with a second refresh time, and for refreshing charge contents of said second test cells with a third refresh time; and
an evaluation unit for detecting memory cell defects in said first test cell area and in said second test cell area;
said first refresh time being shorter than said second refresh time; and
said second refresh time being shorter than said third refresh time.
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Abstract
An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.
16 Citations
18 Claims
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1. An integrated dynamic memory, comprising:
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a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells, said regular memory cells, said first test cells and said second test cells being for storing a charge corresponding to an information bit;
a control unit for refreshing charge contents of said regular memory cells with a first refresh time;
a control unit for refreshing charge contents of said first test cells with a second refresh time, and for refreshing charge contents of said second test cells with a third refresh time; and
an evaluation unit for detecting memory cell defects in said first test cell area and in said second test cell area;
said first refresh time being shorter than said second refresh time; and
said second refresh time being shorter than said third refresh time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for operating an integrated dynamic memory, which comprises:
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providing the integrated dynamic memory with a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells;
providing the regular memory cells, the first test cells and the second test cells for storing a charge corresponding to an information bit;
refreshing charge contents of the regular memory cells with a first refresh time;
writing test patterns to the first test cells and to the second test cells;
refreshing charge contents of the first test cells with a second refresh time, and refreshing charge contents of the second test cells with a third refresh time;
providing the first refresh time being shorter than the second refresh time and providing the second refresh time being shorter than the third refresh time;
reading memory cell contents of thc first test cell area and the second test cell area and detecting memory cell defects by comparing the memory cell contents with the test patterns that were written to the first test cells and to the second test cells; and
checking the first refresh time with regard to the memory cell defects that were detected in the first test cell area and in the second test cell area. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for operating a plurality of integrated dynamic memory modules, which comprises:
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providing each one of the plurality of the integrated dynamic memory modules with;
a memory cell array having a regular cell area with regular memory cells, a first test cell area with first test cells, and a second test cell area with second test cells, the regular memory cells, the first test cells and the second test cells being for storing a charge corresponding to an information bit;
a control unit for refreshing charge contents of the regular memory cells with a first refresh time;
a control unit for refreshing charge contents of the first test cells with a second refresh time, and for refreshing charge contents of the second test cells with a third refresh time; and
an evaluation unit for detecting memory cell defects in the first test cell area and in the second test cell area;
the first refresh time being shorter than the second refresh time; and
the second refresh time being shorter than the third refresh time;
for each one of the plurality of the integrated dynamic memory modules, in response to a request signal from an external controller, determining the first refresh time and communicating the first refresh time to the controller;
using the controller to determine a shortest refresh time selected from a group consisting of the first refresh time, the second refresh time, and the third refresh time; and
subsequently using the shortest refresh time for refreshing each one of the plurality of the integrated dynamic memory modules. - View Dependent Claims (18)
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Specification