Three-dimensional memory array incorporating serial chain diode stack
First Claim
1. A multi-level memory array comprising:
- on alternate levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate and running in a second direction different than the first direction, such that a projection of the rail-stacks on one level to the rail-stacks on an adjacent level defines intersections therebetween; and
a layer of low conducting material separating the rail-stacks on one level from the rail-stacks on an adjacent level, the layer of low conducting material at each intersection of rail-stacks separating a first conductivity type doped semiconductor material in the rail-stack below the intersection from a material other than a first conductivity type doped semiconductor material in the rail-stack above the intersection.
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Accused Products
Abstract
A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
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Citations
41 Claims
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1. A multi-level memory array comprising:
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on alternate levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate and running in a second direction different than the first direction, such that a projection of the rail-stacks on one level to the rail-stacks on an adjacent level defines intersections therebetween; and
a layer of low conducting material separating the rail-stacks on one level from the rail-stacks on an adjacent level, the layer of low conducting material at each intersection of rail-stacks separating a first conductivity type doped semiconductor material in the rail-stack below the intersection from a material other than a first conductivity type doped semiconductor material in the rail-stack above the intersection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A multi-level memory array comprising:
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on alternate levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate and running in a second direction different than the first direction, such that a projection of the conductors on one level to the conductors on an adjacent level defines intersections therebetween; and
a programmable layer of material separating the conductors on one level from the conductors on an adjacent level, the programmable layer of material at each intersection of conductors having a conductivity capable of being modified by application of a voltage and forming, at least before or after the application of the voltage, a steering device between successive levels of conductors;
wherein the steering devices between successive levels of conductors are each oriented in a like direction. - View Dependent Claims (25, 26, 27, 28, 29)
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30. A multi-level non-volatile memory array comprising:
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a plurality of first conductors disposed at a first and third level running generally in a first direction above a substrate;
a plurality of second conductors disposed at a second and fourth level above the substrate and running in a second direction, and a plurality of dielectric regions each disposed respectively between successive levels of the first and second conductors which are capable of being selectively breached to form a diode between successive levels of the first and second conductors;
wherein the resulting diodes between successive levels of the first and second conductors are each oriented in a like direction. - View Dependent Claims (31, 32)
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33. A multi-level non-volatile memory array comprising:
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a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate;
a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, and a plurality of dielectric regions each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to form a diode between successive levels of the first and second rail-stacks;
wherein the resulting diodes between successive levels of the first and second rail-stacks are each oriented in a like direction. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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Specification