Semiconductor device having an external electrode

• US 20030025202A1
• Filed: 07/17/2002
• Published: 02/06/2003
• Est. Priority Date: 07/17/2001
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Furuya, Akira, Hatano, Keisuke, Mikagi, Kaoru
• Application Number:
  US10/197,149
• Publication Number:
  US 20030025202A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

An external electrode in a semiconductor device includes, from the bottom of a wafer, a wiring pad, first and second barrier metal layers, a solder-wetting film and a solder ball. The first barrier metal layer has a tensile internal stress and a granular crystalline structure, whereas the second barrier metal layer has a compressive internal stress and a pillar crystalline structure. The two-layer structure of the barrier metal film has an excellent barrier function against Sn diffusion from the solder ball and reduces the internal stress of the barrier metal film.

Claims

1. A semiconductor device comprising an external electrode having a wiring pad, a barrier metal electrode and a solder ball consecutively formed on a wafer, said barrier metal electrode including a plurality of barrier metal layers having common elements and having different internal stresses and/or different crystalline structures.

4. The semiconductor device as defined in claim 1, wherein said barrier metal layers include a first barrier metal layer having a tensile internal stress and a second barrier metal layer having a compressive internal stress.

5. The semiconductor device as defined in claim 1, wherein said barrier metal layers include a first barrier metal layer having a granular crystalline structure and a second barrier metal layer having a pillar crystalline structure.

6. The semiconductor device as defined in claim 5, wherein said barrier metal layers further include first and second amorphous layers made of nickel or nickel alloy and formed on said first and second barrier metal layers, respectively.

7. The semiconductor device as defined in claim 1, wherein said barrier metal electrode includes a protective layer covering edges of said barrier metal layers.

8. A semiconductor device comprising an external electrode having a wiring pad, a barrier metal electrode and a solder ball consecutively formed on a wafer, said barrier metal electrode including first through fifth conductive films consecutively formed on said wiring pad, wherein said second and fourth conductive films are barrier metal films, and said fourth conductive film is a plating film.

9. The semiconductor device as defined in claim 8, wherein said second conductive film includes a first conductive layer having a granular crystalline structure and a second conductive layer having a pillar crystalline structure.

10. The semiconductor device as defined in claim 9, wherein said second conductive film includes a first conductive layer having a tensile internal stress and a second conductive layer having a compressive internal stress.

11. The semiconductor device as defined in claim 8, wherein said third conductive film includes copper, and said second and fourth conductive films include nickel as a main component thereof.

12. The semiconductor device as defined in claim 8, wherein said fourth conductive film has a thickness larger than a thickness of said second conductive film.

13. The semiconductor device as defined in claim 8, wherein said barrier metal electrode further includes a protective film for covering edge portions of said first through fifth conductive films.

14. A method for manufacturing an external electrode in a semiconductor device, said method comprising the steps of:

forming a wiring pad on a wafer;

forming a plurality of barrier metal layers on said wiring pad; and

forming a solder ball on said barrier metal layers.

2. The semiconductor device as defined in claim 17 wherein said barrier metal layers include nickel or nickel alloy.

3. The semiconductor device as defined in claim 2, wherein said nickel alloy is selected from the group consisting of nickel vanadium, nickel tungsten, nickel tantalum, nickel silicon and nickel copper alloys.

15. The method as defined in claim 14, wherein said plurality of barrier metal layers include nickel or nickel alloy and have different internal stresses.

16. The method as defined in claim 14, wherein said plurality of barrier metal layers include nickel or nickel alloy and have different crystalline structures.

17. The method as defined in claim 14, wherein said plurality of barrier metal layers include an amorphous layer made of nickel or nickel alloy.

18. The method as defined in claim 14, wherein said nickel alloy is selected from the group consisting of nickel vanadium, nickel tungsten, nickel tantalum, nickel silicon and nickel copper alloys.

19. The method as defined in claim 14, wherein said barrier metal layers forming step includes the step of controlling a bias voltage applied to said wafer to control an internal stress or crystalline structure of said barrier metal layers.

20. A method for manufacturing an external electrode in a semiconductor device, said method comprising the steps of:

forming a wiring pad on a wafer;

forming a first barrier metal film made of nickel or nickel alloy on said wiring pad by sputtering in a vacuum ambient;

forming a seed film on said first barrier metal film in said vacuum ambient;

forming a second barrier metal film made of nickel by plating on said seed film; and

forming a solder ball on said second barrier metal film.

21. The method as defined in claim 20, wherein said nickel alloy is selected from the group consisting of nickel vanadium, nickel tungsten, nickel tantalum, nickel silicon and nickel copper alloys.

22. The method as defined in claim 20, wherein said first barrier metal film forming step includes the step of controlling a bias voltage applied to said wafer to control an internal stress or crystalline structure of said first barrier metal film.

23. A semiconductor device comprising an external electrode having a wiring pad, a barrier metal electrode and a solder ball consecutively formed on a wafer, said barrier metal electrode including first through fourth conductive films consecutively formed on said wiring pad, wherein said third conductive films are barrier metal films, and said third conductive film is a plating film.

24. The semiconductor device as defined in claim 23, wherein said second and fourth conductive film includes copper and said a third conductive layer includes nickel as a main component thereof.

25. The semiconductor device as defined in claim 23, wherein said fourth conductive film has a thickness larger than a thickness of said second conductive film.

26. The semiconductor device as defined in claim 23, wherein said barrier metal electrode includes a protective layer covering edges of said barrier metal layers.

27. The semiconductor device as defined in claim 26, wherein said protective layer includes conductive layer or bilayer of conductive layer and dielectric layer.