Switch matrix
First Claim
1. A switch matrix comprising:
- a plurality of first input interconnections (N);
a plurality of second output interconnections (M);
a plurality of input modules (X) wherein each input module comprises a group of input interconnections selected from said plurality of first input interconnections (N), a first plurality of interconnected switches, and a plurality of first output interconnections, wherein the sum of the input interconnections in said groups of input interconnections is equal to the total number of first input interconnections (N);
a plurality of output modules (P), wherein each output module comprises a plurality of second input interconnections, a second plurality of interconnected switches, and a group of output interconnections selected from said plurality of second output interconnections, wherein the sum of the output interconnections in said groups of output interconnections is equal to the total number of second output interconnections (M);
wherein said plurality of first output interconnections is electrically coupled to said plurality of second input interconnections;
wherein said plurality of input modules (X) are electrically coupled to said plurality of output modules (P), to form a plurality of signal paths having a plurality of interconnected switches (K) per signal path.
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Accused Products
Abstract
A switch matrix 10 is provided comprising a plurality of input modules X and a plurality of output modules P. Each input module 16 has a plurality of first input interconnections 14, a plurality of first interconnected switches 21, and a plurality of first output interconnections 20. Each output module 18 has a plurality of second input interconnections 23, a plurality of second interconnected switches 24, and a plurality of second output interconnections 20. The plurality of input modules X is electrically coupled to the plurality of output modules P, forming a plurality of signal paths 12 having a plurality of interconnected switches K per signal path 12. A method is also provided minimizing the total number of interconnected switches Z within the switch matrix 10 for a particular application. The method comprises determining switch matrix design requirements, calculating the values of X and P, and performing an integer partitioning process.
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Citations
21 Claims
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1. A switch matrix comprising:
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a plurality of first input interconnections (N);
a plurality of second output interconnections (M);
a plurality of input modules (X) wherein each input module comprises a group of input interconnections selected from said plurality of first input interconnections (N), a first plurality of interconnected switches, and a plurality of first output interconnections, wherein the sum of the input interconnections in said groups of input interconnections is equal to the total number of first input interconnections (N);
a plurality of output modules (P), wherein each output module comprises a plurality of second input interconnections, a second plurality of interconnected switches, and a group of output interconnections selected from said plurality of second output interconnections, wherein the sum of the output interconnections in said groups of output interconnections is equal to the total number of second output interconnections (M);
wherein said plurality of first output interconnections is electrically coupled to said plurality of second input interconnections;
wherein said plurality of input modules (X) are electrically coupled to said plurality of output modules (P), to form a plurality of signal paths having a plurality of interconnected switches (K) per signal path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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- 14. A system as in claim 14 wherein the value of said P multiplied by the value of said K*P is an integer value.
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16. A method of minimizing the total number of interconnected switches (Z) within a switch matrix having a plurality of first input interconnections (N), a plurality of input modules (X), a plurality of output modules (P), and a plurality of second output interconnections (M) comprising the steps of:
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determining the values of P and X; and
performing an integer partitioning process.
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17. A method according to claim 17 further comprising:
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providing a desired degree of isolation;
providing a desired redundancy capability; and
providing a quantity of interconnected switches (K) per signal path as a function of said degree of isolation and said redundancy capability. - View Dependent Claims (18, 19, 20, 21)
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Specification