Scalable flash/NV structures and devices with extended endurance

• US 20030042534A1
• Filed: 08/30/2001
• Published: 03/06/2003
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 7,012,297 B2
• Time in Patent Office: Days
• US Class Current: 257/317
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

Claims

1. A gate stack, comprising:

a tunnel medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium; and

an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

2. The gate stack of claim 1, wherein the injector medium is disposed on the high K charge blocking and charge storing medium.

3. The gate stack of claim 1, wherein the tunnel medium is disposed on the injector medium.

4. The gate stack of claim 1, wherein the tunnel medium includes tunnel Al₂O₃.

5. The gate stack of claim 1, wherein the tunnel medium includes tunnel SiO₂.

6. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes a high K charge blocking medium disposed on a high K charge storing medium with nano crystals.

7. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes silicon-rich Al₂O₃.

8. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes tantalum.

9. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes titanium.

10. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes zirconium.

11. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes hafnium.

12. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes praseodymium.

13. The gate stack of claim 1, wherein the high K charge blocking and charge storing medium includes BST.

14. The gate stack of claim 1, wherein the injector medium includes injector SRN.

15. The gate stack of claim 1, wherein the injector medium includes injector SRO.

16. The gate stack of claim 1, wherein the injector medium includes silicon rich aluminum nitride.

17. The gate stack of claim 1, wherein the tunnel medium, the high K charge blocking and charge storing medium, and the injector medium are scalable with power supply and lithography scaling.

18. A gate stack, comprising:

a tunnel medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes nano crystals for providing charge trapping charge centers; and

an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

19. The gate stack of claim 18, wherein the nano crystals include silicon nano crystals.

20. The gate stack of claim 18, wherein the nano crystals include gold nano crystals.

21. The gate stack of claim 18, wherein the nano crystals include tungsten nano crystals.

22. The gate stack of claim 18, wherein the nano crystals include silicided nano crystals.

23. A gate stack, comprising:

a first injector medium;

a tunnel medium disposed on the first injector medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium; and

a second injector medium disposed on the high K charge blocking and charge storing medium.

24. The gate stack of claim 23, wherein the first injector medium is disposed on a NO surface treated substrate.

25. The gate stack of claim 23, wherein the first injector medium is disposed on a NH₃ surface treated substrate.

26. The gate stack of claim 23, wherein the tunnel medium is selected from the group consisting of tunnel Al₂O₃ and tunnel SiO₂.

27. The gate stack of claim 23, wherein the injector medium is selected from the group consisting of injector SRN, injector SRO, and silicon rich aluminum nitride.

28. The gate stack of claim 23, wherein the high K charge blocking and charge storing medium includes Al₂O₃.

29. A gate stack, comprising:

a first injector medium;

a tunnel medium disposed on the first injector medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes nano crystals for providing charge trapping charge centers; and

a second injector medium disposed on the high K charge blocking and charge storing medium.

30. The gate stack of claim 29, wherein the nano crystals include silicon nano crystals.

31. The gate stack of claim 29, wherein the nano crystals include gold nano crystals.

32. The gate stack of claim 29, wherein the nano crystals include tungsten nano crystals.

33. The gate stack of claim 29, wherein the nano crystals include silicided nano crystals.

34. A gate stack, comprising:

a tunnel medium;

a high K charge storing medium disposed on the tunnel medium;

a high K charge blocking medium disposed on the high K charge storing medium; and

an injector medium operably disposed with respect to the tunnel medium, the high K charge storing medium and the high K charge blocking medium to provide charge transport by enhanced tunneling.

35. The gate stack of claim 34, wherein the injector medium is disposed on the high K charge blocking medium.

36. The gate stack of claim 34, wherein the tunnel medium is disposed on the injector medium.

37. The gate stack of claim 34, wherein the tunnel medium is selected from the group consisting of tunnel Al₂O₃ and tunnel SiO₂.

38. The gate stack of claim 34, wherein at least one of the high K charge blocking and the high K charge storing medium is selected from the group consisting of Al₂O₃, tantalum, titanium, zirconium, hafnium, praseodymium and BST.

39. The gate stack of claim 34, wherein the injector medium is selected from the group consisting of injector SRN, injector SRO, and silicon rich aluminum nitride.

40. The gate stack of claim 34, wherein the tunnel medium, the high K charge blocking and charge storing medium, and the injector medium are scalable with power supply and lithography scaling.

41. A gate stack, comprising:

a tunnel medium;

a high K charge storing medium disposed on the tunnel medium, wherein the high K charge storing medium includes nano crystals for providing charge trapping charge centers;

a high K charge blocking medium disposed on the high K charge storing medium; and

an injector medium operably disposed with respect to the tunnel medium, the high K charge storing medium and the high K charge blocking medium to provide charge transport by enhanced tunneling.

42. The gate stack of claim 41, wherein the nano crystals include silicon nano crystals.

43. The gate stack of claim 41, wherein the nano crystals include gold nano crystals.

44. The gate stack of claim 41, wherein the nano crystals include tungsten nano crystals.

45. The gate stack of claim 41, wherein the nano crystals include silicided nano crystals.

46. A gate stack, comprising:

a first injector medium disposed on a substrate;

a tunnel medium disposed on the first injector medium;

a high K charge storing medium disposed on the tunnel medium;

a high K charge blocking medium stored on the high K charge storing medium; and

a second injector medium disposed on the high K charge blocking medium.

47. The gate stack of claim 46, wherein the gate stack is disposed on a NO surface treated substrate.

48. The gate stack of claim 46, wherein the gate stack is disposed on a NH₃ surface treated substrate.

49. The gate stack of claim 46, wherein the first and second injector media include injector SRN.

50. The gate stack of claim 46, wherein the first and second injector media include injector SRO.

51. The gate stack of claim 46, wherein the first and second injector media include silicon-rich aluminum nitride.

52. The gate stack of claim 46, wherein the high K charge storing medium includes silicon nano crystals.

53. The gate stack of claim 46, wherein the high K charge storing medium includes gold nano crystals.

54. The gate stack of claim 46, wherein the high K charge storing medium includes tungsten nano crystals.

55. The gate stack of claim 46, wherein the high K charge storing medium includes silicided tungsten nano crystals.

56. A memory cell, comprising:

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium; and

an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

57. The memory cell of claim 56, wherein the injector medium is disposed on the high K charge blocking and charge storing medium.

58. The memory cell of claim 56, wherein the tunnel medium is disposed on the injector medium.

59. The memory cell of claim 56, wherein the tunnel medium includes tunnel Al₂O₃.

60. The memory cell of claim 56, wherein the tunnel medium includes tunnel SiO₂.

61. The memory cell of claim 56, wherein the high K charge blocking and charge storing medium includes a high K charge blocking medium disposed on a high K charge storing medium with nano crystals.

62. The memory cell of claim 56, wherein the high K charge blocking and charge storing medium includes silicon-rich Al₂O₃.

63. The memory cell of claim 56, wherein the injector medium includes injector SRN.

64. The memory cell of claim 56, wherein the injector medium includes injector SRO.

65. The memory cell of claim 56, wherein the injector medium includes silicon rich aluminum nitride.

66. The memory cell of claim 56, wherein the tunnel medium, the high K charge blocking and charge storing medium, and the injector medium are scalable with power supply and lithography scaling.

67. A memory cell, comprising:

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge storing medium disposed on the tunnel medium;

a high K charge blocking medium disposed on the high K charge storing medium; and

an injector medium operably disposed with respect to the tunnel medium, the high K charge storing medium and the high K charge blocking medium to provide charge transport by enhanced tunneling.

68. The memory cell of claim 67, wherein the injector medium is disposed on the high K charge blocking medium.

69. The memory cell of claim 67, wherein the tunnel medium is disposed on the injector medium.

70. The memory cell of claim 67, wherein the tunnel medium includes tunnel Al₂O₃.

71. The memory cell of claim 67, wherein the tunnel medium includes tunnel SiO₂.

72. The memory cell of claim 67, wherein at least one of the high K charge blocking and the high K charge storing medium includes Al₂O₃.

73. A nonvolatile memory device, comprising:

an array of memory cells operably coupled to a grid of row lines and column lines;

row select circuitry for selecting a row of memory cells; and

column select circuitry for selecting a column of memory cells,

wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage; and

wherein each memory cell includes;

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium; and

an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

74. The nonvolatile memory device of claim 73, wherein the injector medium is disposed on the high K charge blocking and charge storing medium.

75. The nonvolatile memory device of claim 73, wherein the tunnel medium is disposed on the injector medium.

76. The nonvolatile memory device of claim 73, wherein the tunnel medium includes tunnel Al₂O₃.

77. The nonvolatile memory device of claim 73, wherein the tunnel medium includes tunnel SiO₂.

78. The nonvolatile memory device of claim 73, wherein the high K charge blocking and charge storing medium includes a high K charge blocking medium disposed on a high K charge storing medium with nano crystals.

79. The nonvolatile memory device of claim 73, wherein the high K charge blocking and charge storing medium includes silicon-rich Al₂O₃.

80. The nonvolatile memory device of claim 73, wherein the injector medium includes injector SRN.

81. The nonvolatile memory device of claim 73, wherein the injector medium includes injector SRO.

82. The nonvolatile memory device of claim 73, wherein the injector medium includes silicon rich aluminum nitride.

83. The nonvolatile memory device of claim 73, wherein the tunnel medium, the high K charge blocking and charge storing medium, and the injector medium are scalable with power supply and lithography scaling.

84. An electronic system, comprising:

a processor; and

a nonvolatile memory device coupled to the processor, the nonvolatile memory device including;

an array of memory cells operably coupled to a grid of row lines and column lines;

row select circuitry for selecting a row of memory cells; and

column select circuitry for selecting a column of memory cells,

wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage; and

wherein each memory cell includes;

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge blocking and charge storing medium disposed on the tunnel medium; and

an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

85. A method of forming a nonvolatile memory cell, comprising:

providing a tunnel medium;

disposing a high K charge blocking and charge store medium on the tunnel medium; and

operably disposing an injector medium with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

86. The method of claim 85, wherein operably disposing an injector medium includes disposing the injector medium on the high K charge blocking and charge store medium.

87. The method of claim 85, wherein operably disposing an injector medium includes disposing the tunnel medium on the injector medium.

88. The method of claim 85, wherein operably disposing an injector medium includes providing a first injector medium and a second injector medium, wherein providing a second injector medium includes disposing the second injector medium on the high K charge blocking and charge store medium, and wherein providing a tunnel medium includes disposing the tunnel medium on the first injector medium.

89. The method of claim 85, wherein disposing a high K charge blocking and charge storing medium on the tunnel medium includes disposing a high K charge storing medium on the tunnel medium and disposing a high K charge blocking medium on the high K charge storing medium.

90. The method of claim 85, wherein disposing a high K charge blocking and charge storing medium on the tunnel medium includes disposing silicon-rich Al₂O₃ on the tunnel medium.

91. The method of claim 85, wherein operably disposing an injector medium includes disposing injector SRN.

92. The method of claim 85, wherein operably disposing an injector medium includes disposing injector SRO.

93. The method of claim 85, wherein operably disposing an injector medium includes disposing silicon-rich aluminum nitride.

94. The method of claim 85, wherein providing a tunnel medium includes providing tunnel Al₂O₃.

95. The method of claim 85, wherein providing a tunnel medium includes providing tunnel SiO₂.

96. A method of forming a nonvolatile memory cell, comprising:

providing a tunnel medium;

disposing a high K charge blocking and charge store medium on the tunnel medium, including dispersing nano crystals in a high K dielectric; and

operably disposing an injector medium with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.

97. The method of claim 96, wherein dispersing nano crystals includes implanting nano crystals.

98. The method of claim 96, wherein dispersing nano crystals includes doping nano crystals.

99. The method of claim 96, wherein dispersing nano crystals includes dispersing silicon nano crystals.

100. The method of claim 96, wherein dispersing nano crystals includes dispersing gold nano crystals.

101. The method of claim 96, wherein dispersing nano crystals includes dispersing tungsten nano crystals.

102. The method of claim 96, wherein dispersing nano crystals includes dispersing silicided tungsten nano crystals.

103. A method of enhancing an electric field across a gate stack in a NV memory cell, comprising:

dispersing nano crystals in a high K dielectric to provide charge trapping charge centers in the high K dielectric; and

providing an injector medium with nano crystals to provide charge transport by enhanced tunneling.

104. The method of claim 103, further comprising providing a contact between a programming electrode and the high K dielectric.

105. The method of claim 103, wherein providing an injector medium includes providing the injector medium between a programming electrode and the high K dielectric.

106. The method of claim 103, wherein providing an injector medium includes providing the injector medium between a tunnel medium and a source electrode.

107. The method of claim 103, wherein providing an injector medium with nano crystals includes providing an injector medium with silicon nano crystals.

108. The method of claim 103, wherein providing an injector medium with nano crystals includes providing an injector medium with gold nano crystals.

109. The method of claim 103, wherein providing an injector medium with nano crystals includes providing an injector medium with tungsten nano crystals.

110. The method of claim 103, wherein providing an injector medium with nano crystals includes providing an injector medium with silicided tungsten nano crystals.

111. The method of claim 103, wherein dispersing nano crystals in a high K dielectric to provide charge trapping charge centers in the high K dielectric includes dispersing silicon nano crystals in Al₂O₃ to form silicon-rich Al₂O₃.

112. The method of claim 103, further comprising providing a high K charge blocking medium and providing a high K charge storing medium, wherein dispersing nano crystals in a high K dielectric forms the high K charge storing medium, and wherein providing a high K charge blocking medium includes disposing the high K charge blocking medium on the high K charge storing medium.

113. The method of claim 112, wherein providing a high K charge blocking medium includes providing blocking Al₂O₃, and wherein providing a high K charge storing medium includes providing silicon-rich Al₂O₃.

114. A method of operating a nonvolatile memory device, comprising:

writing to one or more non-volatile memory cells in one or more arrays by applying a voltage across a high K dielectric to store charge on charge centers in the high K dielectric; and

erasing one or more non-volatile memory cells by applying a voltage across the high K dielectric to tunnel electrons off of the charge centers.

115. The method of claim 114, wherein applying a voltage across a high K dielectric includes enhancing a resulting electric field using at least one injector medium.

116. The method of claim 114, wherein writing to one or more non-volatile memory cells in one or more arrays includes applying a voltage across alumina (Al₂O₃) to store charge on charge centers formed by nano crystals dispersed in the Al₂O₃.

117. An electronic system, comprising:

a plurality of fixed threshold devices for performing random logic functions; and

a plurality of nonvolatile devices operably coupled to the plurality of fixed threshold devices to provide desired logic functions, wherein each of the plurality of nonvolatile devices includes;

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge storing medium disposed on the tunnel medium;

a high K charge blocking medium disposed on the high K charge storing medium; and

an injector medium operably disposed with respect to the tunnel medium, the high K charge storing medium and the high K charge blocking medium to provide charge transport by enhanced tunneling.

118. The electronic system of claim 117, wherein the plurality of fixed threshold devices include an input node, and the plurality of nonvolatile devices are operably coupled to the input node to provide the desired logic functions.

119. The electronic system of claim 118, wherein the plurality of fixed threshold devices and the plurality of nonvolatile devices are deployed as an alterable logic device (ALD).

120. The electronic system of claim 118, wherein the plurality of fixed threshold devices and the plurality of nonvolatile devices are deployed as a programmable logic device (PLD).

121. The electronic system of claim 117, wherein the plurality of fixed threshold devices include an output node, and the plurality of nonvolatile devices are operably coupled to the output node to provide the desired logic functions.

122. The electronic system of claim 121, wherein the plurality of fixed threshold devices and the plurality of nonvolatile devices are deployed as an alterable logic device (ALD).

123. The electronic system of claim 121, wherein the plurality of fixed threshold devices and the plurality of nonvolatile devices are deployed as a programmable logic device (PLD).

124. An electronic system, comprising:

a programmable logic array; and

a nonvolatile programmable memory array (ONVPMA) coupled to the programmable logic array, wherein the NVPMA includes a plurality of logic devices, each of the plurality of logic devices including;

a substrate including diffused regions that form a source region and a drain region;

a gate stack disposed on the substrate between the source region and the drain region; and

a gate disposed on the gate stack,

wherein the gate stack includes;

a tunnel medium;

a high K charge storing medium disposed on the tunnel medium;

a high K charge blocking medium disposed on the high K charge storing medium; and

an injector medium operably disposed with respect to the tunnel medium, the high K charge storing medium and the high K charge blocking medium to provide charge transport by enhanced tunneling.