Multi-master bus architecture for system -on-chip designs

• US 20030043790A1
• Filed: 09/06/2001
• Published: 03/06/2003
• Est. Priority Date: 09/06/2001
• Status: Active Grant

• Current Assignee: Strong Force IoT Portfolio 2016, LLC (Strong Force Intellectual Capital, LLC)
• Original Assignee: MeshNetworks, Inc. (Motorola Solutions, Inc.)
• Inventors: Gutierrez, Philip
• Granted Patent: US 7,145,903 B2
• Time in Patent Office: Days
• US Class Current: 370/362
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves. The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave. The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design. In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves.

Claims

1. A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves, wherein each bus master and each bus slave has at least a port in and a port out, the system comprising:

a plurality of multiplexers in communication with each data in port of each bus master and each bus slave;

a plurality of isolated data paths connecting the port out of each bus master to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design; and

distributed arbitration to allow each bus slave to be selected independently of other bus slaves.

3. The bus architecture system of claim 1 further comprising:

distributed address decoding to allow each master to have a tailored address map.

4. The bus architecture system of claim 3, wherein the distributed address decoding includes an address decoder in communication with each multiplexer that is in communication with the data in port of each bus master.

5. The bus architecture system of claim 1, wherein the bus masters are off chip.

6. The bus architecture system of claim 1, wherein the bus slaves are off chip.

2. The bus architecture system of claim 2, wherein the distributed arbitration includes an arbiter in communication with each multiplexer that is in communication with the data in port of each bus slave.

7. A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves, wherein each bus master and each bus slave has at least a port in and a port out, the system comprising:

a plurality of multiplexers in communication with each data in port of each bus master and each bus slave;

a plurality of isolated data paths connecting the port out of each bus master to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer, of said plurality of multiplexers in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design; and

distributed address decoding to allow each master to have a tailored address map.

8. The bus architecture system of claim 7, wherein the distributed address decoding includes an address decoder in communication with each multiplexer that is in communication with the data in port of each bus master.

9. The bus architecture system of claim 7, further comprising distributed arbitration to allow each bus slave to be selected independently of other bus slaves.

10. The bus architecture system of claim 9, wherein the distributed arbitration includes an arbiter in communication with each multiplexer that is in communication with the data in port of each bus slave.

11. A bus architecture system on an integrated circuit comprising:

a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave;

a plurality of multiplexers in communication with each data in port;

a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; and

an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave.

12. The bus architecture system of claim 11 further comprising:

an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master.

13. The bus architecture system of claim 12 further comprising at least one of the following protocols:

retry condition, data pre-fetch, address and data error recovery, or maximum latency timers.

14. The bus architecture system of claim 11, wherein one or more of the bus masters are off chip.

15. The bus architecture system of claim 11, wherein one or more of the bus slaves are off chip.

18. The bus architecture system of claim 12 or 17 further comprising a single clock controlling the bus architecture system to yield data burst rates greater than 1.6 Gbytes/s per point-to-point connection.

19. The bus architecture system of claim 12 or 17 further comprising a single clock controlling the bus architecture system to yield aggregate data burst rates greater than 10 Gbytes/s per point-to-point connection.

16. A bus architecture system on an integrated circuit comprising:

a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave;

a plurality of multiplexers in communication with each data in port;

a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; and

an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master.

17. The bus architecture system of claim 16 further comprising:

an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave.