VARIABLE LENGTH DECODER FOR DECODING DIGITALLY ENCODED VIDEO SIGNALS

• US 20030043917A1
• Filed: 03/29/1999
• Published: 03/06/2003
• Est. Priority Date: 05/18/1998
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: HONG, JOHN, BOSE, SUBROTO, OZCELIK, TANER, GADRE, SHIRISH C., BUBLIL, MOSHE
• Granted Patent: US 6,704,361 B2
• Time in Patent Office: Days
• US Class Current: 375/240.25
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.

Claims

1. A variable length decoder for decoding a stream of compressed video data, wherein the stream includes a plurality of variable length encoded data representing image areas of transmitted frames, comprising:

a memory for storing variable length encoded data;

a command decode and execution circuit coupled to the memory for receiving selected variable length encoded data from the memory;

a sequencer coupled to the command decode and execution circuit for providing commands to the command decode and execution circuit to convert the variable length encoded data into corresponding decoded values; and

a master controller coupled to the command decode and execution circuit for providing commands to the command decode and execution circuit independently of the sequencer to control decoding operation of the command decode and execution circuit.

2. The variable length decoder of claim 1 wherein the sequencer includes memory for storing a plurality of instructions and an instruction decode and control circuit coupled to the instruction memory for decoding instructions from the memory and providing commands to the command decode and execution circuit to convert the variable length encoded data into corresponding decoded values.

3. The variable length decoder of claim 1 further comprising a plurality of command instruction registers coupled to the sequencer and the master controller, wherein the sequencer and master controller are operable to read and write contents of the command instruction registers.

4. The variable length decoder of claim 3 wherein the command instruction registers are associated with the instructions provided to the command decode and execution circuit.

5. The variable length decoder of claim 1 further comprising a variable length table decoder coupled to the command decode and execution circuit for receiving variable length encoded data and provided a corresponding decoded value to the command decode and execution circuit.

6. The variable length decoder of claim 1 wherein the command decode and execution circuit is operable to decode variable length encoded data conforming to an MPEG syntax.

7. The variable length decoder of claim 6 wherein the command decode and execution circuit is operable to decode the variable length encoded data into DCT coefficient symbols each including a run-length value and an amplitude level value.

8. The variable length decoder of claim 7 further comprising a first-in first-out memory and decoder coupled to the command decode and execution circuit for storing the DCT coefficient symbols as compressed run-length and amplitude level pairs.

9. The variable length decoder of claim 8 further comprising an inverse DCT transform circuit coupled to the first-in first-out memory and decoder, wherein the first-in first-out memory and decoder is operable to decompress the run-length and amplitude level pairs into DCT coefficients for use by the DCT transform circuit in reconstructing image data of the transmitted frames. matches additional data in the variable length encoded data after the identified prefix pattern.

14. The variable length table decoder of claim 13 wherein each of the variable length codes includes an associated code length, and wherein the control circuitry is responsive to the pattern match circuit for obtaining a code length from the subtable data circuit associated with the unique prefix pattern in the variable length codes that matches the identified prefix pattern in the variable length encoded data, and additional data in the variable length codes after the unique prefix pattern that matches additional data in the variable length encoded data after the identified prefix pattern.

15. The variable length table decoder of claim 14 further comprising a shifter circuit associated with the memory for applying a predetermined number of bits of the variable length encoded data from the memory to the pattern match circuit.

16. The variable length table decoder of claim 15 wherein the shifter circuit includes a plurality of selector circuits for selectively shifting the variable length encoded data in the memory.

17. The variable length table decoder of claim 16 wherein the plurality of selector circuits are arranged in a plurality of selector stages, wherein each selector stage is operable to shift the variable length encoded data in memory by a power of two or to provide no shift of the variable length encoded data.

18. The variable length table decoder of claim 17 wherein at least one of the selector stages includes fewer selector circuits than a preceding selector stage.

19. The variable length table decoder of claim 17 wherein each selector stage includes fewer selector circuits than its preceding selector stage.

20. The variable length table decoder of claim 16 wherein the shifter circuit is responsive to the last obtained code value for shifting the variable length encoded data in the memory by a number of bits equal to obtained code value.

21. A method for decoding a stream of compressed video data using variable length code tables, wherein the stream includes a plurality of variable length encoded data representing image areas of transmitted frames, comprising the steps of:

defining a variable length code table including a decoded value associated with each of a plurality of variable length codes;

defining a plurality of unique prefix patterns associated with the variable length codes,

defining a plurality of subtables, wherein each subtable is associated with one of the unique prefix patterns in the variable length codes and includes at least one decoded value that is associated with the unique prefix pattern and additional data in the variable length code after the unique prefix pattern;

identifying in the variable length encoded data one of the unique prefix patterns associated with the variable length codes; and

obtaining a decoded value from the subtable associated with the unique prefix pattern in the variable length codes that matches the identified prefix pattern in the variable length encoded data, and additional data in the variable length codes after the unique prefix pattern that matches additional data in the variable length encoded data after the identified prefix pattern.

22. The method of claim 21 further comprising the steps of:

associating a code length with each of the plurality of variable length codes; and

obtaining a code length associated with the variable length code having a prefix pattern that matches the identified prefix pattern in the variable length encoded data, and additional data after the prefix pattern that matches additional data in the variable length encoded data after the identified prefix pattern.

23. The method of claim 21, further comprising the steps of:

identifying in the variable length encoded data one of the unique prefix patterns associated with the variable length codes; and

simultaneously applying the additional data in the variable length encoded data to each of the plurality of subtables,

wherein a decoded value is obtained from the subtable associated with the unique prefix pattern in the variable length codes that matches the identified prefix pattern in the variable length encoded data, and additional data in the variable length codes after the unique prefix pattern that matches additional data in the variable length encoded data after the identified prefix pattern.