Memory device and method for temperature-based control over write and/or read operations

• US 20030046020A1
• Filed: 08/31/2001
• Published: 03/06/2003
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 6,735,546 B2
• Time in Patent Office: Days
• US Class Current: 702/132
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

The preferred embodiments described herein provide a memory device and method for temperature-based control over write and/or read operations. In one preferred embodiment, the temperature of a memory array is monitored, and a write operation to the memory array is prevented in response to the monitored temperature reaching a threshold temperature. In another preferred embodiment, the temperature of a memory array is monitored, and a read operation from the memory array is prevented in response to the monitored temperature reaching a threshold temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Claims

1. A method for temperature-based control over a write operation to a memory array, the method comprising:

(a) monitoring temperature of a memory array; and

(b) preventing a write operation to the memory array in response to the monitored temperature reaching a threshold temperature.

2. The invention of claim 1, wherein the memory array is formed on a substrate, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor located on the substrate.

3. The invention of claim 1, wherein the memory array is located within a housing of a memory device, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor located within the housing.

4. The invention of claim 3, wherein the housing houses at least one component in addition to the memory array, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor on the at least one component.

5. The invention of claim 1, wherein the act of preventing a write operation in (b) comprises preventing a start of a new write operation.

6. The invention of claim 1, wherein the act of preventing a write operation in (b) comprises allowing an in-progress write operation to end and preventing a start of a new write operation.

7. The invention of claim 1, wherein the act of preventing a write operation in (b) comprises interrupting an in-progress write operation.

8. The invention of claim 1 further comprising:

(c) allowing the write operation to be performed to the memory array in response to the monitored temperature being below the threshold temperature.

9. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises preventing a start of a new write operation, and wherein the act of allowing the write operation to be performed in (c) comprises allowing the start of the new write operation.

10. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises allowing an in-progress write operation to end and preventing a start of a new write operation, and wherein the act of allowing the write operation to be performed in (c) comprises allowing the start of the new write operation.

11. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises interrupting an in-progress write operation, and wherein the act of allowing the write operation to be performed in (c) comprises resuming the in-progress write operation.

12. The invention of claim 1 further comprising:

(c) preventing a read operation from the memory array in response to the monitored temperature reaching a second threshold temperature.

13. The invention of claim 1, wherein the temperature is monitored in (a) with a first temperature sensor, and wherein the invention further comprises:

monitoring temperature of the memory array with a second temperature sensor; and

preventing a read operation from the memory array in response to the monitored temperature from the second temperature sensor reaching a second threshold temperature.

14. The invention of claim 1, wherein the memory array comprises a three-dimensional memory array.

15. The invention of claim 1, wherein the memory array comprises a plurality of antifuse memory cells.

16. The invention of claim 1, wherein the memory array comprises a plurality of write-once memory cells.

17. The invention of claim 1, wherein the memory array comprises a plurality of write-many memory cells.

45. The invention of claim 1, 18, or 35, wherein the threshold temperature comprises a thermal run-away temperature of the memory array.

46. The invention of claim 1, 18, or 35, wherein the threshold temperature comprises a temperature greater than a thermal run-away temperature of the memory array.

18. A method for temperature-based control over a read operation from a memory array, the method comprising:

(a) monitoring temperature of a memory array; and

(b) preventing a read operation from the memory array in response to the monitored temperature reaching a threshold temperature.

19. The invention of claim 18, wherein the memory array is formed on a substrate, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor located on the substrate.

20. The invention of claim 18, wherein the memory array is located within a housing of a memory device, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor located within the housing.

21. The invention of claim 20, wherein the housing houses at least one component in addition to the memory array, and wherein the temperature of the memory array is monitored in (a) with a temperature sensor on the at least one component.

22. The invention of claim 18, wherein the act of preventing a read operation in (b) comprises preventing a start of a new read operation.

23. The invention of claim 18, wherein the act of preventing a read operation in (b) comprises allowing an in-progress read operation to end and preventing a start of a new read operation.

24. The invention of claim 18, wherein the act of preventing a read operation in (b) comprises interrupting an in-progress read operation.

25. The invention of claim 18 further comprising:

(c) allowing the read operation to be performed to the memory array in response to the monitored temperature being below the threshold temperature.

26. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises preventing a start of a new read operation, and wherein the act of allowing the read operation to be performed in (c) comprises allowing the start of the new read operation.

27. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises allowing an in-progress read operation to end and preventing a start of a new read operation, and wherein the act of allowing the read operation to be performed in (c) comprises allowing the start of the new read operation.

28. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises interrupting an in-progress read operation, and wherein the act of allowing the read operation to be performed in (c) comprises resuming the in-progress read operation.

29. The invention of claim 18 further comprising:

(c) preventing a write operation to the memory array in response to the monitored temperature reaching a second threshold temperature.

30. The invention of claim 18, wherein the temperature is monitored in (a) with a first temperature sensor, and wherein the invention further comprises:

monitoring temperature of the memory array with a second temperature sensor; and

preventing a write operation to the memory array in response to the monitored temperature from the second temperature sensor reaching a second threshold temperature.

31. The invention of claim 18, wherein the memory array comprises a three-dimensional memory array.

32. The invention of claim 18, wherein the memory array comprises a plurality of antifuse memory cells.

33. The invention of claim 18, wherein the memory array comprises a plurality of write-once memory cells.

34. The invention of claim 18, wherein the memory array comprises a plurality of write-many memory cells.

35. A memory device comprising:

a memory array;

a temperature sensor; and

write operation control circuitry coupled with the memory array and the temperature sensor and operative to prevent a write operation to the memory array in response to a temperature sensed by the temperature sensor reaching a threshold temperature.

36. The invention of claim 35, wherein the write operation control circuitry is further operative to allow the write operation to be performed in response to the temperature sensed by the temperature sensor being below the threshold temperature.

37. The invention of claim 35 further comprising read operation control circuitry coupled with the memory array and operative to prevent a read operation from the memory array.

38. The invention of claim 37, wherein the read operation control circuitry is operative to prevent the read operation in response to a temperature sensed by the temperature sensor reaching a second threshold temperature.

39. The invention of claim 37 further comprising a second temperature sensor coupled with the read operation control circuitry, and wherein the read operation control circuitry is operative to prevent the read operation in response to a temperature sensed by the second temperature sensor reaching a second threshold temperature.

40. The invention of claim 35, wherein the write-operation control circuitry comprises:

a comparator operative to compare an output of the temperature sensor to a reference voltage;

a pulse signal generator coupled with the comparator and operative to generate a pulse signal with voltage hysteresis; and

an edge triggered flip flop coupled with the pulse signal generator.

41. The invention of claim 35, wherein the memory array comprises a three-dimensional memory array.

42. The invention of claim 35, wherein the memory array comprises a plurality of antifuse memory cells.

43. The invention of claim 35, wherein the memory array comprises a plurality of write-once memory cells.

44. The invention of claim 35, wherein the memory array comprises a plurality of write-many memory cells.