Method for debugging reconfigurable architectures

• US 20030046607A1
• Filed: 09/28/2001
• Published: 03/06/2003
• Est. Priority Date: 09/03/2001
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, May, Frank, Nuckel, Armin
• Granted Patent: US 7,266,725 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.

Claims

1. Method for debugging reconfigurable hardware, wherein all necessary debugging information is written for each configuration cycle into a memory which is then evaluated by the debugger.