Data processing apparatus having DRAM incorporated therein

• US 20030048274A1
• Filed: 10/31/2002
• Published: 03/13/2003
• Est. Priority Date: 03/21/1996
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sato, Jun, Miyamoto, Takashi, Yamagishi, Kazushige
• Granted Patent: US 6,744,437 B2
• Time in Patent Office: Days
• US Class Current: 345/519
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Claims

1. A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated and an image memory in which drawing information is stored, wherein

said image memory includes a plurality of memory modules having a same construction and each allotted with a same row address and are inputted with a column control signal corresponding to a number of said memory modules.

2. A semiconductor integrated device according to claim 1, wherein said image memory includes a plurality of memory modules each composed of a plurality of banks and a number of bits of data lines made active by a same address is the same for each memory module.

3. A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated and first and second image memories each of which has image information stored therein, wherein

read and write operations for said first and second image memories are performed on the basis of an instruction from said image processor and said image processor executes a non-operation instruction after the output of a write address, thereby making the latencies of said read and write operations for said image memories equal to each other.

4. A semiconductor integrated device according to claim 3, wherein

source data is read from said first image memory in a first period of time after a row address is taken in said first image memory,

dot data is read from said second image memory in said first period of time after the row address is taken in said second image memory, and

said image processor synthesizes said source data and said dot data in a second period of time to output an address signal and a control signal, thereby performing the writing into said second image memory.

5. A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated and first and second dynamic RAMs each of which has image information stored therein, wherein

said first dynamic RAM and said second dynamic RAM are simultaneously refreshed and the cycle of refresh is based on said first dynamic RAM.

6. A semiconductor integrated device according to claim 5, wherein a number of refresh cycles and a number of refresh clocks of each of said first and second dynamic RAMs are fixed in said image processor in reference to said first dynamic RAM, thereby unifying the refreshing of the plurality of dynamic RAMs.

7. A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated and an image memory in which image information is stored, wherein

a row address issued from said image processor to said image memory is given by a pipe-line processing, and

a column address issued from said image processor to said image memory is given continuously.

8. A semiconductor integrated device according to claim 7, wherein in the case where a plurality of row addresses are issued from said image processor, said pipe-line processing detects and issues the change-over of the plurality of row addresses at the first stage, pre-charges a memory cell corresponding to the changed-over row address at the next stage, and issues a column address at the final stage.