Selective operation of a multi-state non-volatile memory system in a a binary mode

• US 20030053334A1
• Filed: 08/26/2002
• Published: 03/20/2003
• Est. Priority Date: 09/17/2001
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian
• Granted Patent: US 6,717,847 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

Claims

1. A method of controllably operating a plurality of blocks of non-volatile memory cells in either at least four threshold level states or exactly two threshold level states, wherein said at least four threshold level states are spaced apart across a memory cell operating threshold window and said exactly two threshold level states are those of the four threshold level states that are maximally separated from each other within the operating threshold window.

2. The method of claim 1, wherein the memory cells within at least one of the plurality of blocks is operated in said exactly two threshold level states and the memory cells within at least another one of the plurality of blocks is operated in said at least four threshold level states.

3. The method of claim 2, wherein a table of blocks of memory in which user data are stored is written into memory cells of said at least one of the plurality of blocks that is operated in said exactly two threshold levels, and the user data is stored in memory cells of said at least another one of the plurality of blocks that is operated in said at least four threshold level states.

4. The method of claim 1, wherein at least one of said plurality of blocks of memory cells is initially operated in said at least four threshold level states until a number of erase/programming cycles of said at least one block reaches a predetermined amount, upon which said at least one block is then operated in said at least two threshold level states.

5. In a memory system having a plurality of blocks of non-volatile memory cells that individually stores more than one bit of data in one of at least four threshold level states that are spaced apart across an operating threshold window, a method of operating the memory system comprising storing one bit of data in the memory cells of at least one of the blocks in only two of said at least four threshold level states that are furthest displaced form each other within the operating threshold window.

6. The method of claim 5, which additionally comprises reading data from the individual cells of said at least some of the blocks that are stored in said only two of the four threshold level states by use of a threshold reference having a value intermediate of others of said at least four threshold level states than said only two threshold level states furthest displaced from each other.

7. The method of claim 6, wherein one of said only two threshold level states furthest displaced from each other is an erased state within a negative region of the operating threshold window and said read threshold reference is a non-zero positive voltage.

8. The method of claim 5, wherein the memory system is a NAND system.

9. In a flash non-volatile memory system with memory cells connected in a NAND arrangement, wherein at least two bits are normally programmed into individual ones of the memory cells from at least two different pages of data, a method of programming only one bit into some of the system'"'"'s memory cells comprising programming one bit from one of said at least two pages into individual ones of said some of the system'"'"'s memory cells in the same manner as when normally programmed as one of two bits but without programming the second bit from the other of said at least two pages.