Method and apparatus for implementing precision time delays

• US 20030053572A1
• Filed: 09/20/2001
• Published: 03/20/2003
• Est. Priority Date: 09/20/2001
• Status: Active Grant

• Current Assignee: TDC Acquisition Holdings, Inc (Humatics Corporation)
• Original Assignee: Time Domain Corporation (Humatics Corporation)
• Inventors: Confer, Ryan N., Pendergrass, Marcus H., Brethour, Vernon R.
• Granted Patent: US 6,677,796 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/159 Applications of delay lines not covered by the preceding subgroups
• CPC Class Codes: H04B 1/71632 Signal aspects H04B1/7172 and H04B1/7176 take precedence
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence

Abstract

A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.

Claims

22. A method of implementing precision time delays, comprising the steps of:

splitting a clock input into at least two separate clock inputs with a specified phase shift therebetween;

inputting a delay count into a lookup table, said lookup table providing a first off circle scaling factor to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said lookup table also providing a second off circle scaling factor to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal; and

adding said first multiplied signal to said second multiplied signal and outputing said added signal.

2. The system of implementing precision time delays of claim 1, wherein said first and said second outputs from said lookup table are on circle scaling factors.

3. The system of implementing precision time delays of claim 2, wherein said first and said second outputs from said lookup table are on circle scaling factors and wherein the output of said first and said second digital to analog converter has binary step sizes.

4. The system of implementing precision time delays of claim 3, further comprising an amplitude thresholding means.

5. The system of implementing precision time delays of claim 2, wherein said first and said second outputs from said lookup table are on circle scaling factors and wherein the output of said first and said second digital to analog converter has optimized step sizes.

6. The system of implementing precision time delays of claim 5, further comprising an amplitude thresholding means.

35. The method of implementing precision time delays of claim 22, wherein the output of said fist and said second digital to analog converter has binary step sizes.

23. The method of implementing precision time delays of claim 22, wherein the output of said first and said second digital to analog converter has optimized step sizes.

24. The method of implementing precision time delays of claim 22, further comprising the step of amplifying said added output signal.

25. The method of implementing precision time delays of claim 22, wherein said at least two separate clock inputs are split into two distinct clock inputs.

26. The method of implementing precision time delays of claim 25, wherein said specified phase shift difference is 90 degrees between said two distinct clock inputs.

27. The method of implementing precision time delays of claim 25, wherein a first of said two distinct clock inputs is phase shifted 45 degrees forward and a second of said two distinct clock inputs is phase shifted 45 degrees backward.

28. The method of implementing precision time delays of claim 25, wherein a first of said two distinct clock inputs is not phase shifted and a second of said two distinct clock inputs is phase shifted 90 degrees backward.

29. The method of implementing precision time delays of claim 25, wherein a first of said two distinct clock inputs is not phase shifted and a second of said two distinct clock inputs is phase shifted 90 degrees forward.

30. The method of implementing precision time delays of claim 25, wherein a first of said two distinct clock inputs is phase shifted 90 degrees forward and a second of said two distinct clock inputs is not phase shifted.

31. The method of implementing precision time delays of claim 25, wherein a first of said two distinct clock inputs is phase shifted 90 degrees backward and a second of said two distinct clock inputs is not phase shifted.

32. The method of implementing precision time delays of claim 22, further comprising:

using a variable threshold to receive as one input the output of said addition and output means; and

providing a second lookup table, said second lookup table'"'"'s output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold.

33. A method of implementing precision time delays, comprising the steps of:

splitting a clock input into at least two separate clock inputs with a specified phase shift therebetween;

inputting a delay count into a lookup table, said lookup table providing a first on circle scaling factor to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said lookup table also providing a second off circle scaling factor to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal; and

adding said first multiplied signal to said second multiplied signal and outputing said added signal.

34. The method of implementing precision time delays of claim 34, wherein the output of said first and said second digital to analog converter has optimized step sizes.

1. A system of implementing precision time delays, comprising:

a clock input, said clock input being split into at least two separate clock inputs with a specified phase shift therebetween;

a delay count providing input to a lookup table, said lookup table providing a first output to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said lookup table also providing a second output to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal; and

an addition and output means to add said first multiplied signal to said second multiplied signal and output said added signal.

7. The system of implementing precision time delays of claim 1, wherein said first and said second outputs from said lookup table are off circle scaling factors.

8. The system of implementing precision time delays of claim 7, wherein said first and said second outputs from said lookup table are on circle scaling factors and wherein the output of said first and said second digital to analog converter has binary step sizes.

9. The system of implementing precision time delays of claim 8, further comprising an amplitude thresholding means.

10. The system of implementing precision time delays of claim 7, wherein said first and said second outputs from said lookup table are on circle scaling factors and wherein the output of said first and said second digital to analog converter has optimized step sizes.

11. The system of implementing precision time delays of claim 10, further comprising an amplitude thresholding means.

12. The system of implementing precision time delays of claim 1, wherein said at least two clock inputs are split into two distinct clock inputs.

13. The system of implementing precision time delays of claim 12, wherein said specified phase shift difference is 90 degrees between said two distinct clock inputs.

14. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is phase shifted 45 degrees forward and a second of said two distinct clock inputs is phase shifted 45 degrees backward.

15. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is phase shifted 45 degrees forward and a second of said two distinct clock inputs is phase shifted 45 degrees backward.

16. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is phase shifted 45 degrees forward and a second of said two distinct clock inputs is phase shifted 45 degrees backward.

17. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is not phase shifted and a second of said two distinct clock inputs is phase shifted 90 degrees backward.

18. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is not phase shifted and a second of said two distinct clock inputs is phase shifted 90 degrees forward.

19. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is phase shifted 90 degrees forward and a second of said two distinct clock inputs is not phase shifted.

20. The system of implementing precision time delays of claim 13, wherein a first of said two distinct clock inputs is phase shifted 90 degrees backward and a second of said two distinct clock inputs is not phase shifted.

21. The system of implementing precision time delays of claim 1, further comprising:

a variable threshold, said variable threshold receiving as one input the output of said addition and output means; and

a second lookup table, said second lookup table'"'"'s output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold.

35-1. The method of implementing precision time delays of claim 34, wherein the output of said first and said second digital to analog converter has binary step sizes.

35-2. The method of implementing precision time delays of claim 22, further comprising the step of amplifying said added output signal.