Thin film semiconductor device containing polycrystalline Si-Ge alloy and method for producing thereof

• US 20030054593A1
• Filed: 10/22/2002
• Published: 03/20/2003
• Est. Priority Date: 02/01/2001
• Status: Active Grant

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated)
• Inventors: Shiba, Takeo, Hatano, Mutsuko, Park, Seong-Kee, Yamaguchi, Shinya
• Granted Patent: US 6,690,064 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

The present invention relates to a thin film transistor, in a low-temperature poly-Si thin film becoming an elemental material of the thin film transistor, an object of the invention is to provide the thin film transistor suitable for realizing an image display device having a high performance and a large area at low cost by realizing a poly-crystalline thin film having a crystal structure restraining current scattering in a grain boundary, lessening surface roughness, and capable of realizing high mobility even to a positive hole current.

The object described above is achieved by realizing a TFT with high mobility by restraining a current scattering factor in a grain boundary of crystal with an introduction of Ge into the poly-crystalline Si thin film and with a difference in ratios of Ge compositions between an interior grain of crystal and a grain boundary of crystal resulted from a phase separation involved in crystallization, and by restraining surface roughness using a difference in volumes in a crystal.

Claims

1. A thin film transistor device comprising:

(a) an insulator substrate;

(b) a poly-crystalline thin film formed on said insulator substrate; and

(c) a transistor composed of a source, a drain, a channel, and a gate formed on said poly-crystalline thin film,

wherein said poly-crystalline thin film in a channel part of said transistor is composed of a silicon-germanium poly-crystalline Si_1-xGe_x, however, a ratio x of a Ge composition relative to Si is 0<

x<

1, and a ratio x of a Ge composition in the poly-crystalline thin film is larger in a grain boundary than a portion where a Ge composition in an interior grain of crystal becomes the minimum.

2. A thin film transistor device as set forth in claim 1, wherein a thickness of said poly-crystalline thin film is 10-100 nm, a ratio x of a Ge composition in a portion where a Ge composition being the minimum in an interior grain of crystal constituting said poly-crystalline thin film is 0<

x≦

0.3, a ratio x of a Ge composition in a grain boundary is 0.1<

x≦

1.0, and a ratio x of the Ge composition described above is invariably large in a grain boundary than a central part of a crystal grain.

3. A thin film transistor device as set forth in claim 1, wherein said poly-crystalline Si_1-xGe_x has surface roughness thereof in a grain boundary being equal to or less than 30 nm.

4. A thin film transistor device as set forth in claim 1, wherein a main current carried in a channel part of said transistor is a positive hole.

6. A thin film transistor device comprising:

(a) an insulator substrate;

(b) a poly-crystalline Si_1-xGe_x thin film formed on said insulator substrate, however, a ratio x of a Ge composition relative to Si is 0<

x<

1; and

(c) a circuit part constituted by integrating a plurality of pieces of transistors composed of sources, drains, channels, and gates formed on said poly-crystalline Si_1-xGe_x thin film,

wherein, said circuit part is composed of CMOS type transistors making present as a mixture of p type transistors and n type transistors, and at least said p type transistor is constituted of the transistor as set forth in claim 1.

5. A thin film transistor device comprising:

(a) an insulator substrate;

(b) a poly-crystalline thin film formed on said insulator substrate; and

(c) a transistor composed of a source, a drain, a channel, and a gate formed on said poly-crystalline thin film,

wherein said poly-crystalline thin film in a channel part of said transistor has a {110}-oriented crystal surface and an average lattice constant in a grain boundary is larger than an average lattice constant in an interior, grain part of crystal.

7. A method for producing a thin film transistor device comprising steps of:

(a) forming an amorphous Si_1-xGe_x layer of a film thickness of 10-100 nm on an insulator substrate with, however, a ratio x of a Ge composition relative to Si being 0<

x<

1; and

(b) being subjected to a heat treatment for crystallizing the amorphous Si_1-xGe_x layer by an excimer laser with an energy density of 200-300 mJ/cm² and the pulse number of 1-50 pieces.

8. A method for producing a thin film transistor device as set forth in claim 7, wherein said step of heat treatment varies the energy density as (180+T)˜

(200+T) mJ/cm² according to a film thickness when the film thickness of said amorphous Si_1-xGe_x layer is set as T nm.

9. An image display device comprising:

(a) an image display part;

(b) an image display circuit controlling a display of said image display part and including at least a data driver, a gate driver, and a buffer amplifier; and

(c) a peripheral circuit part positioned in the neighborhood of said image display circuit and controlling said image display circuit,

wherein said image display circuit and said peripheral circuit part are integrated on the same substrate as the substrate constituting said image display device, said image display circuit and said peripheral circuit part further comprise an insulator substrate, a poly-crystalline Si_1-xGe_x thin film formed on said insulator substrate, however, a ratio x of a Ge composition relative to Si is 0<

x<

1, and a circuit part constituted by integrating a plurality of pieces of transistors constituted of sources, drains, channels, and gates formed on said poly-crystalline Si_1-xGe_x thin film, and said circuit part includes a CMOS type transistor making present as a mixture either one or both of p type transistors or/and n type transistors.

10. An image display device as set forth in claim 9 wherein a ratio x of a Ge composition of a p type transistor constituting said circuit part is larger than a ratio of a Ge composition of an n type transistor.

11. An image display device as set forth in claim 9 or claim 10 wherein said circuit part comprises positioning marks provided in the neighborhood of these circuits in order to differentiate whichever sorts of the p type transistor, n type transistor, and the CMOS type transistor.