Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)

• US 20030056085A1
• Filed: 05/28/2002
• Published: 03/20/2003
• Est. Priority Date: 12/09/1996
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Entire Interest
• Inventors: Vorbach, Martin, Munch, Robert
• Granted Patent: US 7,237,087 B2
• Time in Patent Office: Days
• US Class Current: 712/32
• CPC Class Codes: B01J 19/088 giving rise to electric discharges for heating purposes H05B7/00; for the production of ozone C01B13/11, H01T19/00
• CPC Class Codes: B01J 2219/0849 Corona pulse discharge
• CPC Class Codes: C01B 13/11 by electric discharge
• CPC Class Codes: C01B 2201/22 Constructional details of the electrodes
• CPC Class Codes: C01B 2201/24 Composition of the electrodes
• CPC Class Codes: C01B 2201/32 Constructional details of the dielectrics
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate
• CPC Class Codes: Y10S 422/907 Corona or glow discharge means

Abstract

An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it. A power-saving mode which shuts down the cell can be configured through the function register; clock rate dividers which reduce the working frequency can also be set.

Claims

1. :

Configurable unit that can be reconfigured at run time for processing numerical and logic operations (PAE) for use in central processing units (CPUs), multi-computer systems, data flow processors (DFPs), digital signal processors (DSPs), systolic processors and field programmable gate arrays (FPGAs) controlled by a primary logic unit (PLU), characterized in that

1. there is a programmable arithmetic and logic unit (EALU) for performing the basic mathematical and logic functions,

2. the function and interconnection of the central processor are programmed in registers and various data can be processed without reprogramming the PAE,

3. there is a state machine (SM UNIT) for controlling the arithmetic and logic unit (EALU),

4. there are registers for each operand (O-REG) and the result (R-REG), some of the registers being designed as shift registers,

5. there is feedback of the data of the result register to an input of the EALU over a multiplexer (R2O-MUX),

6. a bus unit (BM UNIT) permits pick-up of data from a bus system and feeding the result to a bus system, the bus unit being capable of sending data to multiple receivers and the synchronization of multiple receivers taking place automatically,

7. the bus access from the data processing in the EALU is decoupled via the registers and thus each PAE can be regarded as an independent unit, in particular the configuration and reconfiguration of a PAE have no interfering effect on the data transmitters and receivers or on the independent PAEs,

8. the sequence of bus transfers is controlled automatically over a state machine (sync UNIT), for which purpose handshake lines oRDY, oACK, rRDY and rACK are available,

9. feedback is sent to the PLU for detection of the processing status and reconfigurability of the PAE (state-back UNIT).

2. :

Unit according to claim 1, characterized in that the data processing of a PAE can be stopped (STOP entry in F-PLUREG) and the PAE then indicates its readiness for reconfiguration (ReConfig) after completing the data processing currently underway.

3. :

Unit according to claim 1, characterized in that there are power-saving modes

in which the PAE always operates only when operands from the data transmitter are ready at the input and the result has already been accepted by the receiver, and the PAE otherwise remains inactive without a clock pulse,

in which partial areas of the PAE which are irrelevant for the execution of the data processing currently underway are separated from the clock pulse supply and/or the power supply,

in which the PAE is separated from the power supply.