Semiconductor device

• US 20030057503A1
• Filed: 09/25/2002
• Published: 03/27/2003
• Est. Priority Date: 09/26/2001
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Bungo, Yoneda, Tatsuo
• Granted Patent: US 6,690,061 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductive type;

a first semiconductor layer of the first conductive type formed on a main surface of said semiconductor substrate, the impurity concentration of said first semiconductor layer being lower than that of said semiconductor substrate;

a second and third semiconductor layers of a second conductive type formed on said first semiconductor layer, said second and third semiconductor layers being isolated from each other;

a first MOS transistor of the first conductive type formed in said second semiconductor layer, said first semiconductor layer and said semiconductor substrate serving as drains of said first MOS transistor;

a second MOS transistor of the first conductive type formed in said third semiconductor layer, said first semiconductor layer and said semiconductor substrate serving as drains of said second MOS transistor; and

a conductive layer formed on a reverse surface of said semiconductor substrate.

2. The semiconductor device according to claim 1, wherein:

said first MOS transistor includes a gate electrode formed, via a gate insulating film, in a trench formed in said second semiconductor layer so as to reach said first semiconductor layer, and source regions provided near a surface of said second semiconductor layer at both sides of said trench, said source regions contacting said trench; and

said second MOS transistor includes a gate electrode formed, via a gate insulating film, in a trench formed in said third semiconductor layer so as to reach said first semiconductor layer, and source regions provided near a surface of said third semiconductor layer at both sides of said trench, said source regions contacting said trench.

3. The semiconductor device according to claim 2, wherein:

each of said first and second MOS transistors includes a plurality of said gate electrodes and a plurality of said source regions;

said source regions of each of said first and second MOS transistors are covered by a common metal layer; and

solder balls for drawing source electrodes are formed on the metal layer.

4. The semiconductor device according to claim 3, wherein said gate electrodes of each of said first and second MOS transistors are commonly connected.

5. The semiconductor device according to claim 3, further comprising:

a fourth semiconductor layer of the second conductive type, provided near the surface of said second semiconductor layer between adjacent gate electrodes of said first MOS transistor and between source regions corresponding to the adjacent gate electrodes, the impurity concentration of said fourth semiconductor layer being higher than that of said second semiconductor layer; and

a fifth semiconductor layer of the second conductive type, provided near the surface of said third semiconductor layer between adjacent gate electrodes of said second MOS transistor and between source regions corresponding to the adjacent gate electrodes, the impurity concentration of said fifth semiconductor layer being higher than that of said third semiconductor layer.

6. The semiconductor device according to claim 5, wherein said fourth and fifth semiconductor layers are covered by said common metal layer.

7. The semiconductor device according to claim 1, wherein said first semiconductor layer is an epitaxial layer.

8. The semiconductor device according to claim 1, wherein said conductive layer is formed of a vanadium-nickel-gold alloy or aluminum.