Variable pixel clock electronic shutter control

• US 20030062582A1
• Filed: 07/22/2002
• Published: 04/03/2003
• Est. Priority Date: 07/20/2001
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Blerkom, Daniel Van
• Granted Patent: US 7,084,914 B2
• Time in Patent Office: Days
• US Class Current: 257/443
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

CMOS image sensor with a rolling shutter that uses two separate clocks. One of the clocks is used during normal operation. When timing is changed, the other clock is started and used during an interim period to avoid distortion in the image. After that interim period, the new clock timing is coupled to the original clock circuit.

Claims

1. A CMOS image sensor, comprising:

an array of image sensing elements;

a controller for said array of image sensing elements, which produces clock signals to control said array of image sensing elements and which produces first clock signals to control a time of integration beginning, and second clock signals at a second time to control a time of integration ending, said controller controlling said first clock signals to be produced at a same time as said second time for a different row during normal operation, and enabling control of clock-changing operation to set said first clock signal to be produced at a time different than said second time.

2. A sensor as in claim 1, wherein said controller includes first and second clock producing elements, said first clock producing element normally producing said first and second clock signals, and said second clock producing element producing an additional clock signal used as said different time.

3. A sensor as in claim 2, wherein said additional clock signal is formed according to specified formation characteristics, and said formation characteristics of said additional clock signal are used to drive said first clock producing elements during a clock period after an interim clock period.

4. A sensor as in claim 1, wherein said array of image sensing elements and said controller are formed of CMOS semiconductors.

5. An image sensor, comprising

an array of image sensing elements;

a controller for said array of image sensing elements, producing a rolling shutter and outputting first clock signals to control said array of image sensing elements; and

a second clock generating elements associated with said controller, which produces a second clock pulse signal during a time-when said rolling shutter is being changed from a first characteristic to a second characteristic, and outputting said second clock signal at the same time as said first clock signals during an interim frame period, and thereafter using said second clock signal as a new rolling shutter.

6. An image sensor as in claim 5, wherein said array of image sensing elements and controller are formed from CMOS.

7. An image sensor as in claim 5, wherein said controller includes a processor which is programmed to produce said first and second clock signals.

8. A sensor as in claim 5, wherein said controller produces said rolling shutter such that each integration time starting signal is synchronized with an integration time ending signal for a different row.

9. A sensor as in claim 5, wherein said second clock generating element produces signals which cause said integration time starting signal to be synchronized with a different integration time ending signal, for a different row.

10. A sensor as in claim 9, wherein said rolling shutter includes a readout pointer and a shutter pointer, with a start of each row readout time being established by the shutter pointer.

11. A sensor as in claim 10, wherein said shutter pointer resets values within a specified row.

12. A sensor as in claim 9, wherein said first clock signals and said second clock signals operate at different clock speeds.

13. A method, comprising:

controlling an image sensor using a first clock and a second clock which are different;

using said first clock for starting integration times during a first frame, and using said second clock to end integration times during said first frame; and

using said first clock to start and end integration times during a second flame, subsequent to said first frame.

14. A method as in claim 13, further comprising establishing a readout pointer at a top of a current frame plus an offset.

15. A method as in claim 14, wherein said offset

16. A method as in claim 13, wherein said image sensor is a CMOS image sensor.

17. A method as in claim 13, wherein said first clock is offset for each of a plurality of rows, to set start and end timing for said each of said plurality of rows.