Process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensions

• US 20030064558A1
• Filed: 08/20/2002
• Published: 04/03/2003
• Est. Priority Date: 11/26/1999
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Grossi, Alessandro, Clementi, Cesare
• Granted Patent: US 6,603,171 B2
• Time in Patent Office: Days
• US Class Current: 438/201
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Claims

1. A process for manufacturing electronic devices including memory cells, comprising:

on a substrate of semiconductor material, forming stacks including a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material;

forming a protective layer of insulating material extending on top of said substrate and between said stacks, said protective layer having a height at least equal to that of said stacks;

wherein forming stack structures comprises defining said control gate region in two non-parallel directions so that each control gate region is separate and electrically insulated with respect to the control gate regions belonging to adjacent stack structures;

such that, during said forming a protective layer, said stack structures are completely isolated with respect to one another in said two directions;

and further comprising forming word lines of conductive material that extend above said protective layer and that are in electrical contact with said control gate regions.

2. The process of claim 1, wherein said forming word lines comprises:

forming a conductive material layer on top of said stack structures and of said protective layer, said conductive material layer contacting said control gate regions; and

shaping said conductive material layer to form said word lines and electrical interconnections.

3. The process of claim 1, wherein said forming a protective layer comprises depositing an insulating material layer and planarizing said insulating material layer level with said control gate regions.

4. The process of claim 1, comprising forming conductive regions on top of and within said substrate, and after said forming a protective layer, forming openings in said protective layer, said openings extending from one surface of said protective layer as far as said conductive regions, and covering walls of said openings with said conductive material layer.

5. The process of claim 4, wherein said conductive material layer is of tungsten.

6. The process of claim 1, wherein forming stack structures comprises:

forming a composite layer comprising a first semiconductor material layer;

a dielectric material layer on top of said first semiconductor material layer; and

a second semiconductor material layer on top of said dielectric material layer;

shaping said composite layer so as to form multilayer strips extending in a first direction of said two directions; and

shaping said multilayer strips in a second direction of said two directions, said second direction being perpendicular to said first direction.

7. The process of claim 6, comprising, before said forming stack structures:

forming at least one first insulating material layer on top of said substrate; and

defining said first insulating material layer so as to obtain insulating strips extending in said first direction on a first area of said substrate;

and said shaping said multilayer strips in a second direction comprises selectively removing said insulating strips from substrate portions in said first area.

8. The process of claim 7, comprising, after said shaping said multilayer strips, introducing doping ionic species into said substrate portions and forming diffused, elongated source and drain regions extending parallel to and alternating with one another.

9. The process of claim 8, further comprising forming contact regions across said protective layer as far as ends of said diffused, elongated source and drain regions, said contact regions extending externally to said first area.

10. The process of claim 7, comprising, before said forming insulating strips on said first area, making a hard mask having openings on said first area, and forming trenches in a second area of said substrate separate from said first area;

and wherein forming insulating strips comprises depositing a field material layer filling said trenches and said openings, and of selectively removing said field material layer on top of said hard mask and on top of said trenches so as to simultaneously form said insulating strips on said first area and insulating regions on said second area;

said insulating strips in said first area having a different height from said insulating regions in said second area.

11. The process of claim 10, comprising making electronic components in said second area.

12. A process for manufacturing electronic devices, comprising forming first insulating regions and second insulating regions in a first area and, respectively, in a second area separate from said first area, of a substrate of semiconductor material, the process further comprising:

forming a hard mask having openings on said first area;

forming trenches in said second area;

depositing an insulating material layer filling said trenches and said openings; and

selectively removing said insulating material layer on top of said hard mask and on top of said trenches so as to simultaneously form said first insulating regions and said second insulating regions;

said first insulating regions in said first area having a different height from said second insulating regions in said second area.

13. An electronic device comprising:

a substrate of semiconductor material;

memory cells, each including a stack on top of said substrate;

each of said stacks comprising a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material; and

a protective layer extending on top of said substrate and between said stack structures, said protective layer having a height at least equal to that of said stack structures; and

word lines of conductive material extending on top of said insulating material layer;

said control gate region is physically separated from control gate regions belonging to adjacent stack structures by said protective layer;

and said word lines extend on top of said control gate regions and are in electrical contact with said control gate regions.

14. The device of claim 13, comprising interconnection lines of metal, and said word lines comprise metal regions coplanar with said interconnection lines.

15. The device of claim 14, wherein said interconnection lines and said word lines are formed of tungsten.

16. The device of claim 13, wherein said stack structures extend on top of a first portion of said substrate and the device comprises diffused source and drain lines extending parallel to and alternating with one another, at a distance, in said substrate between rows of said stack structures, said diffused source and drain lines having one end that extends in a second portion of said substrate that is remote from said first portion and being electrically connected to source and drain contacts.

17. The device of claim 13, comprising first insulating regions and second insulating regions in a first area and, respectively, in a second area, separate from said first area, of a substrate of semiconductor material, wherein said first insulating regions are formed on top of said substrate and have a first height, and said second insulating regions are formed in trenches extending within said substrate and protrude from said trenches at a second height smaller than said first height.

18. A process for manufacturing electronic devices on a substrate of semiconductor material, comprising:

forming a control gate region in two nonparallel directions on a stack formed of an intermediate dielectric region on top of a floating gate region;

surrounding each stack with a protective layer of nonconductive material; and

forming a word line of conductive material above the protective layer and in electrical contact with the control gate region.

19. A process for manufacturing electronic devices on a substrate of semiconductor material, comprising:

forming a multilayer strip in a first direction on the substrate, the multilayer strip comprising a first semiconductor material layer formed on the substrate of semiconductor material, a dielectric material layer formed on top of the first semiconductor material layer, and a second semiconductor material layer formed on top of said dielectric material layer;

introducing doping ionic species into the semiconductor substrate on each side of the multilayer strip to form diffused, elongated source and drain regions extending parallel to and alternating one with another;

removing portions of the multilayer strip to form isolated multilayer stacks;

forming a protective layer of nonconductive material around the multilayer stacks to completely isolate the multilayer stacks with respect to each other;

forming a word line of conductive material that extend above the protective layer and in electrical contact with the second semiconductor material layer; and

forming contact regions across the protective layer and in electrical contact with the diffused, elongated source and drain regions.