Inklayer image with transparency

• US 20030067469A1
• Filed: 09/13/2002
• Published: 04/10/2003
• Est. Priority Date: 10/09/2001
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Soroushi, Atousa
• Application Number:
  US10/243,608
• Publication Number:
  US 20030067469A1
• Time in Patent Office: Days
• US Class Current: 345/519
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

An inklayer image transparency system of the present invention has a graphics controller or processor, memory, and a display device that may be external to the inklayer image transparency system. The graphics controller is suitable for receiving signals (e.g. an address signal and a transparency control signal) and for providing image information to the display device. The memory is divided into at least two memory sections including a first memory section for storing foreground image information and a second memory section for storing background image information. A single address signal received by the graphics controller is used for simultaneously fetching the foreground image information from the first memory section and the background image information from the second memory section. A transparency control signal having a nontransparent state and a transparent state is used to control whether the foreground image or background image is displayed. The foreground image information is sent for display on the display device when the transparency control signal is in the nontransparent state and the background image information is sent for display on the display device when the transparency control signal is in the transparent state.

Claims

1. An inklayer image transparency system for use with an external system, wherein said external system includes at least one display device for displaying at least one image using a plurality of pixels, said inklayer image transparency system comprising:

(a) a controller suitable for receiving signals and for providing image information to said display device;

(b) for each pixel of said plurality pixels, at least one of said signals being an address signal and at least one of said signals being a transparency control signal;

(c) memory functionally associated with said controller;

(d) said memory divided into at least two memory sections including a first memory section and a second memory section;

(e) said first memory section for storing foreground image information for display on said display device;

(f) said second memory section for storing background image information for display on said display device;

(g) said address signal for simultaneously fetching said foreground image information from said first memory section and said background image information from said second memory section; and

(h) said transparency control signal having a nontransparent state and a transparent state;

(i) said foreground image information being sent for display on said display device when said transparency control signal is in said nontransparent state; and

(ii) said background image information being sent for display on said display device when said transparency control signal is in said transparent state.

2. The inklayer image transparency system of claim 1 wherein said controller and said memory are on a single chip.

3. The inklayer image transparency system of claim 1 wherein said controller is separate from said memory.

4. The inklayer image transparency system of claim 1 wherein said memory is Static Random Access Memory.

5. The inklayer image transparency system of claim 1 wherein said first memory section and said second memory section are independently updatable.

6. The inklayer image transparency system of claim 1 wherein said first memory section is an upper memory section and said second memory section is a lower memory section.

7. The inklayer image transparency system of claim 1 wherein said first memory section is a lower memory section and said second memory section is an upper memory section.

8. The inklayer image transparency system of claim 1 wherein said first memory section has a first memory section size and said second memory section has a second memory section size, said first memory section size being equal to said second memory section size.

9. The inklayer image transparency system of claim 8 wherein said first memory section size and said second memory section size are programmable.

10. A system comprising:

(a) a display device for displaying at least one image having a plurality of pixels;

(b) a processor suitable for receiving signals and for providing information to said display device;

(c) for each pixel of said plurality pixels, at least one of said signals being an address signal and at least one of said signals being a control signal;

(d) memory functionally associated with said processor;

(e) said memory divided into at least two memory sections including a first memory section and a second memory section;

(f) said first memory section for storing first information for display on said display device;

(g) said second memory section for storing second information for display on said display device;

(h) said address signal for simultaneously fetching said first information from said first memory section and said second information from said second memory section; and

(i) said control signal for controlling whether said first information or said second information is displayed on said display device.

11. The system of claim 10 wherein said memory is Static Random Access Memory.

12. The system of claim 10 wherein said first memory section and said second memory section are independently updatable.

13. The system of claim 10 wherein said first memory section is an upper memory section and said second memory section is a lower memory section.

14. The system of claim 10 wherein said first memory section is a lower memory section and said second memory section is an upper memory section.

15. The system of claim 10 wherein said first information is a foreground image and said second information is a background image.

16. The system of claim 10 wherein said first information is a background image and said second information is a foreground image.

17. The system of claim 10 wherein said first memory section has a first memory section size and said second memory section has a second memory section size, said first memory section size being equal to said second memory section size.

18. The system of claim 17 wherein said first memory section size and said second memory section size are programmable.

19. A controller for use with an external system, wherein said external system includes at least one display device for displaying at least one image having a plurality of pixels, said controller comprising:

(a) said controller suitable for receiving signals and for providing information to said display device;

(b) for each pixel of said plurality pixels, at least one of said signals being an address signal and at least one of said signals being a control signal;

(c) memory functionally associated with said controller;

(d) said memory divided into at least two memory sections including a first memory section and a second memory section;

(e) said first memory section for storing first information for display on said display device;

(f) said second memory section for storing second information for display on said display device;

(g) said address signal for simultaneously fetching said first information from said first memory section and said second information from said second memory section; and

(h) said control signal for controlling whether said first information or said second information is displayed on said display device.

20. The controller of claim 19 wherein said controller and said memory are on a single chip.

21. The controller of claim 19 wherein said controller is separate from said memory.

22. The controller of claim 19 wherein said memory is Static Random Access Memory.

23. The controller of claim 19 wherein said first memory section and said second memory section are independently updatable.

24. The controller of claim 19 wherein said first memory section is an upper memory section and said second memory section is a lower memory section.

25. The controller of claim 19 wherein said first memory section is a lower memory section and said second memory section is an upper memory section.

26. The controller of claim 19 wherein said first information is a foreground image and said second information is a background image.

27. The controller of claim 19 wherein said first information is a background image and said second information is a foreground image.

28. The controller of claim 19 wherein said first memory section has a first memory section size and said second memory section has a second memory section size, said first memory section size being equal to said second memory section size.

29. The controller of claim 28 wherein said first memory section size and said second memory section size are programmable.

31. The method of claim 24 wherein said step of determining whether said first information or said second information is to be displayed on said display device based on a control signal further comprises the step of determining whether said first information is transparent.

30. A method for processing graphic display signals and displaying an image based on said graphic display signals on a display device, said display device having a plurality of pixels, said method comprising the steps of:

(a) providing a memory divided into at least two memory sections including a first memory section and a second memory section, said first memory section for storing first information for display on said display device, said second memory section for storing second information for display on said display device;

(b) for each pixel of said plurality of pixels;

(i) determining that an inklayer mode is enabled;

(ii) fetching simultaneously using a single address signal both said first information from said first memory section and said second information from said second memory section;

(iii) determining, based on a control signal, whether said first information or said second information is to be displayed on said display device as a resulting graphic display signal; and

(iv) sending said resulting graphic display signal to said display device.