Decoupling capacitor for high frequency noise immunity

• US 20030072126A1
• Filed: 08/30/2001
• Published: 04/17/2003
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 6,700,771 B2
• Time in Patent Office: Days
• US Class Current: 361/311
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/3143 composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/94 : Metal-insulator-semiconductors, e.g. MOS

Abstract

Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al₂O₃. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.

Claims

1. A capacitor insulator structure, comprising:

a high K dielectric layer; and

nano crystals dispersed through the high K dielectric.

2. The capacitor insulator structure of claim 1, wherein the high K dielectric layer includes alumina (Al₂O₃).

3. The capacitor insulator structure of claim 1, wherein the nano crystals include gold nano crystals.

4. The capacitor insulator structure of claim 1, wherein the nano crystals include silicon nano crystals.

5. The capacitor insulator structure of claim 1, wherein the nano crystals are uniformly distributed in the high K dielectric layer.

6. The capacitor insulator structure of claim Al, wherein the high K dielectric layer includes alumina (Al₂O₃) doped with another high K dielectric.

7. A capacitor, comprising:

a substrate;

a high K dielectric layer doped with nano crystals disposed on the substrate; and

a top plate layer disposed on the high K dielectric layer.

8. The capacitor of claim 7, wherein the substrate is a silicon substrate.

9. The capacitor of claim 7, wherein the high K dielectric layer includes alumina (Al₂O₃) doped with nano crystals.

10. The capacitor of claim 7, wherein the high K dielectric layer doped with nano crystals includes a layer of Al₂O₃ doped with gold nano crystals.

11. The capacitor of claim 7, wherein the high K dielectric layer with nano crystals includes a layer of Al₂O₃ doped with silicon nano crystals.

12. The capacitor of claim 7, wherein the nano crystals are uniformly distributed in the high K dielectric layer.

13. A capacitor, comprising:

a silicon substrate;

a layer of alumina (Al₂O₃) doped with nano crystals disposed on the substrate;

a layer of Silicon-Rich-Nitride (SRN) disposed on the layer of Al₂O₃; and

a silicon top plate disposed on the layer of SRN.

14. The capacitor of claim 13, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with gold nano crystals.

15. The capacitor of claim 13, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with silicon nano crystals.

16. The capacitor of claim 13, wherein the layer of SRN has a thickness of approximately 5 nm.

17. The capacitor of claim 13, wherein the silicon top plate includes a polysilicon top plate.

18. The capacitor of claim 13, wherein the nano crystals are uniformly distributed in the layer of Al₂O₃.

19. The capacitor of claim 13, wherein the layer of Al₂O₃ is further doped with a transition metal.

20. A capacitor, comprising:

a silicon substrate;

a layer of alumina (Al₂O₃) doped with nano crystals disposed on the substrate; and

a layer of titanium nitride (TiN) disposed on the layer of Al₂O₃.

21. The capacitor of claim 20, wherein the layer of TiN functions as a top plate for the capacitor.

22. The capacitor of claim 20, further comprising a metal top plate disposed on the layer of Al₂O₃.

23. The capacitor of claim 20, wherein the layer of TiN has a thickness of about 5 nm.

24. The capacitor of claim 20, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with gold nano crystals.

25. The capacitor of claim 20, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with silicon nano crystals.

26. The capacitor of claim 20, wherein the layer of Al₂O₃ is further doped with a transition metal.

27. A capacitor, comprising:

a substrate;

a layer of alumina (Al₂O₃) doped with nano crystals and at least one transition metal disposed on the substrate; and

a top plate layer disposed on the layer of Al₂O₃.

28. The capacitor of claim 27, wherein the at least one transition metal includes hafnium (Hf).

29. The capacitor of claim 27, wherein the at least one transition metal includes tantalum (Ta).

30. The capacitor of claim 27, wherein the at least one transition metal includes zirconium (Zr).

31. The capacitor of claim 27, wherein the at least one transition metal includes praseodymium (Pr).

32. A capacitor, comprising:

a substrate;

a layer of alumina (Al₂O₃) doped with nano crystals and a high K dielectric disposed on the substrate; and

a top plate layer disposed on the layer of Al₂O₃.

33. The capacitor of claim 32, wherein the high K dielectric includes barium strontium titanate (BST).

34. The capacitor of claim 32, wherein the high K dielectric includes tantalum pentoxide (Ta₂O₅).

35. The capacitor of claim 32, wherein the high K dielectric includes titanium dioxide (TiO₂).

36. The capacitor of claim 32, wherein the high K dielectric includes tantalum nitride (TaN).

37. The capacitor of claim 32, wherein the high K dielectric includes zirconium oxide (ZrO₂).

38. The capacitor of claim 32, wherein the high K dielectric includes praseodymium oxide (Pr₂O₃).

39. A capacitor, including:

a first metal layer;

a layer of alumina (Al₂O₃) disposed on the first metal layer; and

a second metal layer disposed on the layer of Al₂O₃.

40. The capacitor of claim 39, wherein the first metal layer is disposed on silicon.

41. The capacitor of claim 39, wherein the first metal layer includes titanium nitride (TiN).

42. The capacitor of claim 39, wherein the first metal layer includes tungsten (W).

43. The capacitor of claim 39, wherein the first metal layer includes tungsten silicide (WSi).

44. The capacitor of claim 39, wherein the first metal layer includes aluminum (Al).

45. The capacitor of claim 39, wherein the first metal layer includes copper (Cu).

46. The capacitor of claim 39, wherein the layer of Al₂O₃ is doped with nano crystals.

47. The capacitor of claim 39, wherein the second metal layer includes titanium nitride (TiN).

48. The capacitor of claim 39, wherein the second metal layer includes aluminum (Al).

49. The capacitor of claim 39, wherein the second metal layer includes copper (Cu).

50. The capacitor of claim 39, wherein the second metal layer includes tungsten (W)

51. A capacitor, including:

a first metal layer;

a layer of alumina (Al₂O₃) doped with nano crystals disposed on the first metal layer; and

a second metal layer disposed on the layer of Al₂O₃.

52. The capacitor of claim 51, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with gold nano crystals.

53. The capacitor of claim 51, wherein the layer of Al₂O₃ doped with nano crystals includes a layer of Al₂O₃ doped with silicon nano crystals.

54. A capacitor, including:

a first metal layer;

a layer of alumina (Al₂O₃) doped with nano crystals and with at least one transition metal disposed on the substrate disposed on the first metal layer; and

a second metal layer disposed on the layer of Al₂O₃.

55. The capacitor of claim 54, wherein the at least one transition metal includes hafnium (Hf).

56. The capacitor of claim 54, wherein the at least one transition metal includes tantalum (Ta).

57. The capacitor of claim 54, wherein the at least one transition metal includes zirconium (Zr).

58. The capacitor of claim 54, wherein the at least one transition metal includes praseodymium (Pr).

59. A capacitor, including:

a first metal layer;

a layer of alumina (Al₂O₃) doped with nano crystals and a high K dielectric disposed on the substrate disposed on the first metal layer; and

a second metal layer disposed on the layer of Al₂O₃.

60. The capacitor of claim 59, wherein the high K dielectric includes barium strontium titanate (BST).

61. The capacitor of claim 59, wherein the high K dielectric includes tantalum pentoxide (Ta₂O₅).

62. The capacitor of claim 59, wherein the high K dielectric includes titanium dioxide (TiO₂).

63. The capacitor of claim 59, wherein the high K dielectric includes tantalum nitride (TaN).

64. The capacitor of claim 59, wherein the high K dielectric includes zirconium oxide (ZrO₂).

65. The capacitor of claim 59, wherein the high K dielectric includes praseodymium oxide (Pr₂O₃).

66. An integrated circuit, comprising:

a power source;

an integrated circuit load coupled to the power source, the integrated circuit load being characterized by a resonance impedance and a resonance frequency, the integrated circuit load including an inductive load, a resistive load, and a capacitive load; and

a lossy decoupling capacitor coupled to the integrated circuit load to lower the resonance impedance and the resonance frequency, the lossy decoupling capacitor having a large capacitance per unit area (high K value) and a built-in controlled resistance, the lossy decoupling capacitor including;

a high K dielectric layer doped with nano crystals disposed on a substrate; and

a top plate layer disposed on the high K dielectric layer.

67. The integrated circuit of claim 66, wherein the substrate is a silicon substrate.

68. The integrated circuit of claim 66, wherein the high K dielectric layer doped with nano crystals includes a layer of Al₂O₃ doped with gold nano crystals.

69. The integrated circuit of claim 66, wherein the high K dielectric layer doped with nano crystals includes a layer of Al₂O₃ doped with silicon nano crystals.

70. The integrated circuit of claim 66, wherein the nano crystals are uniformly distributed in the high K dielectric layer.

71. The integrated circuit of claim 66, further comprising a layer of Silicon-Rich-Nitride (SRN) disposed on the high K dielectric layer, wherein the top plate layer includes a silicon top plate layer disposed on the layer of SRN.

72. An integrated circuit, comprising:

a power source;

an integrated circuit load coupled to the power source, the integrated circuit load being characterized by a resonance impedance and a resonance frequency, the integrated circuit load including an inductive load, a resistive load, and a capacitive load; and

a lossy decoupling capacitor coupled to the integrated circuit load to lower the resonance impedance and the resonance frequency, the lossy decoupling capacitor having a large capacitance per unit area (high K value) and a built-in controlled resistance, the lossy decoupling capacitor including;

a first metal layer;

a high K dielectric layer disposed on the first metal layer; and

a second metal layer disposed on the high K dielectric layer.

73. The integrated circuit of claim 72, wherein the first metal layer is disposed on silicon.

74. The integrated circuit of claim 72, wherein the first metal layer includes titanium nitride (TiN).

75. The integrated circuit of claim 72, wherein the first metal layer includes tungsten (W).

76. The integrated circuit of claim 72, wherein the first metal layer includes tungsten silicide (WSi).

77. The integrated circuit of claim 72, wherein the high K dielectric layer includes a layer of alumina (Al₂O₃) doped with gold nano crystals.

78. The integrated circuit of claim 72, wherein the high K dielectric layer includes a layer of alumina (Al₂O₃) doped with silicon nano crystals.

79. The integrated circuit of claim 72, wherein the second metal layer includes titanium nitride (TiN).

80. The integrated circuit of claim 72, wherein the second metal layer includes aluminum (Al).

81. The integrated circuit of claim 72, wherein the second metal layer includes A copper (Cu).

82. The integrated circuit of claim 72, further comprising a layer of TiN disposed on the layer of Al₂O₃.

83. The integrated circuit of claim 72, wherein the layer of TiN functions as the top plate layer for the capacitor.

84. The integrated circuit of claim 72, wherein the layer of TiN is disposed between the layer of Al₂O₃ and the top plate layer.

85. A method of forming a Metal-Insulator-Silicon (MIS) decoupling capacitor, comprising:

providing a silicon substrate;

providing a layer of alumina (Al₂O₃) doped with nano crystals on the substrate; and

providing a top plate layer on the layer of Al₂O₃.

86. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes providing a layer of Al₂O₃ doped with gold nano crystals on the substrate.

87. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes providing a layer of Al₂O₃ doped with silicon nano crystals on the substrate.

88. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes uniformly distributing the nano crystals in the layer of Al₂O₃.

89. The method of claim 85, wherein providing a top plate layer on the layer of Al₂O₃ includes providing a layer of Silicon-Rich-Nitride (SRN) disposed on the layer of Al₂O₃ and providing a silicon top plate on the layer of SRN.

90. The method of claim 85, wherein providing a layer of SRN disposed on the layer of Al₂O₃ includes depositing SRN to a thickness of approximately 5 nm.

91. The method of claim 85, wherein providing a top plate layer on the layer of Al₂O₃ includes providing a layer of titanium nitride (TiN) on the layer of Al₂O₃.

92. The method of claim 85, wherein providing a top plate layer on the layer of Al₂O₃ includes providing a layer of TiN on the layer of Al₂O₃ and providing a metal layer on the layer of TiN.

93. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes simultaneous sputtering of the Al₂O₃ and the nano crystals onto the substrate.

94. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes implanting the nano crystals into the layer of Al₂O₃.

95. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes depositing the layer of Al₂O₃ and nano crystals using a vapor phase deposition process.

96. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes depositing Al₂O₃ doped with silicon nano crystals using a chemical vapor deposition (CVD) technique.

97. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes depositing Al₂O₃ doped with silicon nano crystals using an ion beam deposition technique.

98. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes depositing Al₂O₃ doped with silicon nano crystals using an electron cyclotron resonance—

plasma enhanced chemical vapor deposition (ECR-PECVD) technique.

99. The method of claim 85, wherein providing a layer of Al₂O₃ doped with nano crystals on the substrate includes depositing Al₂O₃ doped with silicon nano crystals using a low temperature co-sputtering technique.

100. A method of forming a Metal-Insulator-Silicon (MIS) decoupling capacitor, comprising:

providing a silicon substrate;

providing a layer of alumina (Al₂O₃) on the substrate, including;

doping the layer of Al₂O₃ with nano crystals; and

doping the layer of Al₂O₃ with a transition metal; and

providing a top plate layer on the layer of Al₂O₃.

101. The method of claim 100, wherein doping the layer of Al₂O₃ with a transition metal includes doping the layer of Al₂O₃ with hafnium (Hf).

102. The method of claim 100, wherein doping the layer of Al₂O₃ with a transition metal includes doping the layer of Al₂O₃ with tantalum (Ta).

103. The method of claim 100, wherein doping the layer of Al₂O₃ with a transition metal includes doping the layer of Al₂O₃ with zirconium (Zr).

104. The method of claim 100, wherein doping the layer of Al₂O₃ with a transition metal includes doping the layer of Al₂O₃ with praseodymium (Pr).

105. A method of forming a Metal-Insulator-Silicon (MIS) decoupling capacitor, comprising:

providing a silicon substrate;

providing a layer of alumina (Al₂O₃) on the substrate, including;

doping the layer of Al₂O₃ with nano crystals; and

doping the layer of Al₂O₃ with another high K dielectric; and

providing a top plate layer on the layer of Al₂O₃.

106. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with barium strontium titanate (BST).

107. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with tantalum pentoxide (Ta₂O₅).

108. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with titanium dioxide (TiO₂).

109. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with tantalum nitride (TaN).

110. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with zirconium oxide (ZrO₂).

111. The method of claim 105, wherein doping the layer of Al₂O₃ with a high K dielectric includes doping the layer of Al₂O₃ with praseodymium oxide (Pr₂O₃).

112. A method of forming a Metal-Insulator-Metal (MIM) capacitor at an interconnect level on top of silicon, comprising:

providing an electrode;

providing a layer of alumina (Al₂O₃) on the electrode;

doping the layer of Al₂O₃ with nano crystals; and

providing a metal top plate on the layer of Al₂O₃.

113. The method of claim 112, wherein providing a layer of Al₂O₃ on the electrode includes depositing a layer of Atomic Layer Deposition (ALD) aluminum on the electrode, and oxidizing the layer of ALD aluminum in ozone plasma at low temperature.

114. The method of claim 112, wherein providing a layer of Al₂O₃ on the electrode includes depositing a layer of Al₂O₃ by ion beam deposition.

115. The method of claim 112, wherein providing a layer of Al₂O₃ on the electrode includes depositing a layer of Al₂O₃ by sputtering.

116. The method of claim 112, wherein providing a layer of Al₂O₃ on the electrode includes depositing a layer of Al₂O₃ by electron cyclotron resonance—

plasma enhanced chemical vapor deposition (ECR-PECVD).

117. The method of claim 112, wherein providing an electrode includes providing a titanium nitride (TiN) electrode.

118. The method of claim 112, wherein providing an electrode includes providing a tungsten (W) electrode.

119. The method of claim 112, wherein providing an electrode includes providing a tungsten silicide (WSi) electrode.

120. The method of claim 112, wherein providing an electrode includes providing a copper (Cu) electrode.

121. The method of claim 112, wherein providing an electrode includes providing an aluminum (Al) electrode.

122. The method of claim 112, wherein doping the oxidized layer of ALD aluminum with nano crystals includes doping the oxidized layer of ALD aluminum with gold nano crystals.

123. The method of claim 112, wherein doping the oxidized layer of ALD aluminum with nano crystals includes doping the oxidized layer of ALD aluminum with silicon nano crystals.

124. The method of claim 112, wherein providing a metal top plate on the layer of oxidized ALD aluminum includes providing a titanium nitride (TiN) top plate.

125. The method of claim 112, wherein providing a metal top plate on the layer of oxidized ALD aluminum includes providing an aluminum (Al) top plate.

126. The method of claim 112, wherein providing a metal top plate on the layer of oxidized ALD aluminum includes providing a copper (Cu) top plate.

127. The method of claim 112, wherein providing a metal top plate on the layer of oxidized ALD aluminum includes providing a tungsten (W) top plate.

128. The method of claim 112, further comprising doping the oxidized layer of ALD aluminum with at least one transition metal.

129. The method of claim 112, further comprising doping the oxidized layer of ALD aluminum with a complex high K dielectric.

130. A method of reducing a resonance impedance and a resonance frequency for an integrated circuit chip, comprising:

forming a decoupling capacitor, including;

providing a first plate for a decoupling capacitor;

providing a dielectric for the decoupling capacitor, including forming a layer of alumina (Al₂O₃) doped with nano crystals; and

providing a second plate for the decoupling capacitor such that the dielectric is disposed between the first plate and the second plate; and

coupling the decoupling capacitor to the integrated circuit.

131. The method of claim 130, wherein forming a layer of Al₂O₃ doped with nano crystals includes forming a layer of Al₂O₃ doped with gold nano crystals.

132. The method of claim 130, wherein forming a layer of Al₂O₃ doped with nano crystals includes forming a layer of Al₂O₃ doped with silicon nano crystals.

133. The method of claim 130, further comprising doping the layer of Al₂O₃ with at least one transition metal.

134. The method of claim 130, further comprising doping the layer of Al₂O₃ with a complex high K dielectric.

135. A method of operating a decoupling capacitor, comprising:

applying a voltage across a high K dielectric, and

providing a controlled conductance through the high K dielectric to provide a controlled resistance using a tailored amount of nano crystals uniformly dispersed in the high K dielectric.

136. The method of claim 135, wherein applying a voltage across a high K dielectric includes applying a voltage across alumina (Al₂O₃).

137. The method of claim 135, providing a controlled conductance through the high K dielectric includes using a tailored amount of gold nano crystals uniformly dispersed in the high K dielectric to provide a controlled resistance.

138. The method of claim 135, providing a controlled conductance through the high K dielectric includes using a tailored amount of silver nano crystals uniformly dispersed in the high K dielectric to provide a controlled resistance.