Correction of code drift in a non-coherent memory
First Claim
1. A method of correcting for code drift in a non-coherent memory of a pseudorandom noise receiver, where the non-coherent memory stores non-coherent accumulations of correlation in elements of the non-coherent memory, the method comprising:
- receiving a time index signal, where the time index signal relates to addresses of elements of the non-coherent memory;
receiving an offset signal, where the offset signal is approximately related to an inverse of a product of a frequency computation associated with the non-coherent memory and a number of elements per code chip;
applying the time index signal to the time offset signal to generate a compensated signal;
applying the compensated signal to the non-coherent memory to retrieve a first accumulation;
summing the first accumulation with a sample to generate a second accumulation; and
storing the second accumulation in the non-coherent memory.
1 Assignment
0 Petitions
Accused Products
Abstract
An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous detection of multiple frequencies allows the receiver to search the frequency range of the transmitted signal in larger increments of frequency, thereby increasing the speed of acquisition. One receiver does not use coherent integration before computation of the transform and advantageously maintains a flat frequency response. The flat frequency response of the DFT circuit enables searching of multiple frequency offsets without CPU intensive processing to compensate for frequency response variations. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively fewer addresses or tap positions in memory.
11 Citations
12 Claims
-
1. A method of correcting for code drift in a non-coherent memory of a pseudorandom noise receiver, where the non-coherent memory stores non-coherent accumulations of correlation in elements of the non-coherent memory, the method comprising:
-
receiving a time index signal, where the time index signal relates to addresses of elements of the non-coherent memory;
receiving an offset signal, where the offset signal is approximately related to an inverse of a product of a frequency computation associated with the non-coherent memory and a number of elements per code chip;
applying the time index signal to the time offset signal to generate a compensated signal;
applying the compensated signal to the non-coherent memory to retrieve a first accumulation;
summing the first accumulation with a sample to generate a second accumulation; and
storing the second accumulation in the non-coherent memory. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A Doppler correction circuit that corrects for code drift in a non-coherent memory of pseudorandom noise receiver, where the non-coherent memory stores non-coherent accumulations of correlation in elements of the non-coherent memory, the Doppler correction circuit comprising:
-
means for receiving a time index signal, where the time index signal relates to addresses of elements of the non-coherent memory;
means for receiving an offset signal, where the offset signal is approximately related to an inverse of a product of a frequency computation associated with the non-coherent memory and a number of elements per code chip;
means for applying the time index signal to the time offset signal to generate a compensated signal;
means for applying the compensated signal to the non-coherent memory to retrieve a first accumulation;
means for summing the first accumulation with a sample to generate a second accumulation; and
means for storing the second accumulation in the non-coherent memory.
-
-
9. A synchronizing circuit that compensates for code drift over time in at least a portion of a non-coherent integration memory, the synchronizing circuit comprising:
-
an offset occurrence circuit adapted to receive a clock signal and to provide an indication with a period related to an inverse of a product of a frequency computation associated with the at least portion of the non-coherent integration memory;
a counter circuit adapted to accumulate indications provided by the offset occurrence circuit, where an output of the counter circuit is termed a time offset signal; and
an adder circuit adapted to sum a time index signal with the time offset signal, where the time index signal relates to a memory address with no code drift, where an output of the adder circuit is applied to the address of the non-coherent integration memory such that a memory location indicated by the output of the adder circuit is synchronized with the code. - View Dependent Claims (10, 11, 12)
-
Specification