Silicon on insulator device and layout method of the same

• US 20030080385A1
• Filed: 10/25/2002
• Published: 05/01/2003
• Est. Priority Date: 10/29/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Inventors: Kimura, Yoshitaka
• Granted Patent: US 6,815,771 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Claims

1. A semiconductor device comprising:

a silicon on insulator substrate having an active layer;

at least one doped region formed in the active layer and that constitutes a source/drain region of a MOS transistor; and

an antenna wire formed in an antenna wiring layer, the antenna wire being electrically connected to the at least one doped region directly or through at least one connecting wire in at least one lower wiring layer below the antenna wiring layer,

wherein a ratio of a total area of the antenna wire to a total area of the at least one doped region is limited within a range so that one of plasma processes to pattern the antenna wiring layer and to deposit an interlayer dielectric film covering the antenna wiring layer does not damage the MOS transistor.

2. A semiconductor device comprising:

a silicon on insulator substrate having an active layer;

at least one doped region formed in the active layer and that constitutes a source/drain region of a MOS transistor;

an antenna wire formed in an antenna wiring layer, the antenna wire being electrically connected to the at least one doped region directly or through at least one connecting wire in at least one lower wiring layer below the antenna wiring layer; and

an interlayer dielectric film covering the antenna wiring layer having at least one connection hole for connecting to the antenna wire,

wherein a ratio of a total area of the at least one connection hole to a total area of the at least one doped region is limited within a range so that a plasma process to form the connecting hole does not damage the MOS transistor.

3. A semiconductor device comprising:

a silicon on insulator substrate having an active layer;

at least one doped region formed in the active layer;

an antenna wire formed in an antenna wiring layer, the antenna wire being electrically connected to the at least one doped region directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer; and

a dummy doped region formed in the active layer electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer.

4. The semiconductor device according to claim 3, wherein the at least one doped region constitutes a source/drain region of a MOS transistor.

5. The semiconductor device according to claim 3, wherein the dummy doped region is used only as a capacitor element.

6. A layout method of a semiconductor device comprising:

placing at least one doped region in an active layer of a silicon on insulator substrate;

placing an antenna wire in an antenna wiring layer electrically connected to the at least one doped region directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer; and

when a ratio of a total area of the antenna wire to a total area of the at least one doped region exceeds a predetermined value, performing at least one of;

adding a dummy doped region in the active layer electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;

adding a junction diode electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;

dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and

dividing one of the antenna wire and the at least one first connecting wire into two parts, and inserting a buffer between the two parts.

7. The method according to claim 6, wherein the at least one doped region is placed to form a source/drain region of a MOS transistor.

8. The method according to claim 6, wherein said performing adds the dummy doped region.

9. The method according to claim 8, wherein the dummy doped region is used only as a capacitor element.

10. A layout method of a semiconductor device comprising:

placing at least one doped region in an active layer of a silicon on insulator substrate;

placing an antenna wire in an antenna wiring layer electrically connected to the at least one doped region directly or though at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer;

placing at least one connection hole for connecting to the antenna wire; and

when a ratio of a total area of the at least one connection hole to a total area of the at least one doped region exceeds a predetermined value, performing at least one of;

adding a dummy doped region in the active layer electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;

adding a junction diode electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer;

dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and

dividing one of the antenna wire and the at least one first connecting wire into two parts and inserting a buffer between the two parts.

11. The method according to claim 10, the at least one doped region is placed to form a source/drain region of a MOS transistor.

12. The method according to claim 10, wherein said performing adds the dummy doped region.

13. The method according to claim 12, wherein the dummy doped region is used only as a capacitor element.

14. A method of forming a silicon on insulator device that includes a MOS transistor, the method comprising:

providing a silicon on insulator substrate having an active layer isolated from a semiconductor substrate by a buried oxide film;

forming a field oxide film in the active layer;

removing a portion of the field oxide film and a corresponding portion the buried oxide film to form an opening to expose a portion of a surface of the semiconductor substrate; and

simultaneously forming a doped region in the surface of the exposed portion of the semiconductor substrate and a source and a drain region of the MOS transistor in the active layer.

15. The method according to claim 14, wherein the field oxide film is formed such that a bottom of the field oxide film reaches the buried oxide film.