Semiconductor system-in-package

• US 20030080400A1
• Filed: 03/08/2002
• Published: 05/01/2003
• Est. Priority Date: 10/26/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shioga, Takeshi, Taniguchi, Osamu, Omote, Koji, Yamagishi, Yasuo, Imanaka, Yoshihiko, Okamoto, Keishiro
• Granted Patent: US 7,176,556 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

Claims

1. A semiconductor apparatus, comprising:

a support substrate having through holes flues with conductor in conformity with a first pitch,

a capacitors formed on or above said support substrate,

a wiring layer formed on or above said support, leading some of said through holes filles with conductor upwards via said capacitor, having branches, and having wires of a second pitch different from said first pitch, and

plural semiconductor elements disposed on or above said wiring layer, having terminals in conformity with the second pitch, and connected with said wiring layer via said terminals.

2. The semiconductor apparatus, according to claim 1, further comprising a circuit board having wiring of a first pitch and connected to lower surfaces of said through holes filles with conductor.

3. The semiconductor apparatus, according to claim 1, wherein said second pitch is narrower than said first pitch.

4. The semiconductor apparatus, according to claim 1, wherein said support substrate is a Si substrate having through holes with an insulation film formed on the side walls of the holes, and said through holes filles with conductor are metallic conductors packed in said through holes.

5. The semiconductor apparatus, according to claim 2, wherein said support substrate is a Si substrate having through holes with an insulation film formed on the side walls of the holes, and said through holes filles with conductor are metallic conductors packed in said through holes.

6. The semiconductor apparatus, according to claim 4, wherein said insulation film is a silicon oxide film formed by thermal oxidation, and upper and lower surfaces of said silicon substrate are also covered with a silicon oxide film.

7. The semiconductor apparatus, according to claim 1, wherein said capacitor is a decoupling capacitor connected between power wires, and said wiring layer has branches between said decoupling capacitor and at least one of said semiconductor elements.

8. The semiconductor apparatus, according to claim 1, wherein said through holes filles with conductor include a first signal wire;

said wiring layer contains a second signal wire for leading the first signal wire substantially vertically; and

said capacitor has electrodes with a vacancy around a region where said second signal wire is located.

9. The semiconductor apparatus, according to claim 5, wherein said through holes filles with conductor include a first signal wire;

said wiring layer contains a second signal wire for leading the first signal wire substantially vertically; and

said capacitor has electrodes with a vacancy around a region where said second signal wire is located.

10. The semiconductor apparatus, according to claim 1, further comprising an insulation layer disposed on said support substrate, having a thermal expansion coefficient of 10 ppm/°

C. or less in the in-plane direction, and insulating said wiring layer and said capacitor.

11. The semiconductor apparatus, according to claim 1, wherein said capacitor has a capacitor dielectric layer made of an oxide containing at least one of Ba, Sr and Ti, and a pair of capacitor electrodes sandwiching the capacitor dielectric layer and containing at least partially one of Pt, Ir, Ru, Pd or any of their oxides.

12. The semiconductor apparatus, according to claim 9, wherein said capacitor has a capacitor dielectric layer made of an oxide containing at least one of Ba, Sr and Ti, and a pair of capacitor electrodes sandwiching the capacitor dielectric layer and containing at least partially one of Pt, Ir, Ru, Pd or any of their oxides.

13. The semiconductor apparatus, according to claim 1, wherein said wiring layer contains a wiring connecting said plural semiconductor elements with each other.

14. The semiconductor apparatus, according to claim 1, further comprising another circuit part connected with said wiring layer.

15. A process for producing a semiconductor apparatus, comprising the steps of:

(a)forming through holes at a first pitch in a support substrate;

(b)forming an insulation layer on side walls of said through holes;

(c) filling through holes filles with conductor in the through holes provided with said insulation film;

(d) forming a capacitor connected with at least some of said through holes flues with conductor, and wires connected with said through conductor or said capacitor and having a second pitch, on said support substrate, and

(e)connecting plural semiconductor elements having terminals in conformity with said second pitch, with said wires.

16. The process for producing a semiconductor apparatus, according to claim 15, wherein said support substrate is a Si substrate;

said step (a) thermally oxidizes both surfaces of the Si substrate to form silicon oxide films, and forms through holes passing from one of the silicon oxide films through the silicon substrate to reach the other silicon oxide film;

said step (b) thermally oxidizes side walls of the through holes; and

said step (c)forms a seed layer on back surface of the other silicon oxide film, and removes oxide films at bottoms of the through holes, to expose the seed layer, and forms a plating layer in the through holes using said seed layer as seed.

17. The process for producing a semiconductor apparatus, according to claim 16, wherein said step (d) forms a lower electrode layer, patterns the lower electrode layer to form signal wires and vacancies around them, forms an oxide dielectric film covering the lower electrode, patterns the oxide dielectric film to expose the signal wires and connecting portion of the lower electrode, forms an upper electrode layer covering the oxide dielectric film, and patterns the upper electrode layer to form signal wires, a wire connected with the lower electrode and vacancies around the wires.

18. The process for producing a semiconductor apparatus, according to claim 17, wherein said step (d) further alternately forms an insulation layer and a wiring layer to form a wiring layer adapted to a second pitch.

19. The process for producing a semiconductor apparatus, according to claim 18, wherein said step (d) forms a wiring layer containing wires connecting plural semiconductor elements with each other.

20. The process for producing a semiconductor apparatus, according to claim 15, further comprising the step of connecting said support substrate with a circuit board having wires adapted to said first pitch.