Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
First Claim
1. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:
- a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.
28 Citations
69 Claims
-
1. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:
-
a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being coupled to receive the mode select signal and an array select signal, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A system for selecting between first and second arrays of memory cells each of which includes a set of row lines, the system comprising:
-
a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to receive a row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to receive a column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
an array control circuit coupled to the row lines of the first and second arrays, the array control circuit being coupled to receive the mode select signal and an array select signal, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first and second arrays responsive to the mode select signal indicating operation in the first mode, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first array but not to a row line in the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the array control circuit being operable to allow the row activate signal to be applied to a row line in the second array but not to a row line in the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A memory addressing system for addressing a memory bank having first and second arrays, each of which includes a set of row lines, the memory addressing system comprising:
-
a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal prior to generating the plurality of column address bits, the array select signal corresponding to a column address bit and having either a first state or a second state;
a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode;
a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
-
-
31. A memory device, comprising:
-
a row address circuit operable to receive row address signals applied to an external terminal and to decode the row address signals to generate a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column address circuit operable to receive column address signals applied to an external terminal and to decode the column address signals to generate a column activate signal at one of a plurality of output terminals corresponding to the column address;
first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines;
a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal;
a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal; and
a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode; and
an array control circuit coupled to the row lines of the first and second arrays, the array control circuit being coupled to receive the mode select signal and an array select signal, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first and second arrays responsive to the mode select signal indicating operation in the first mode, the array control circuit being operable to allow the row activate signal to be applied to a row line in the first array but not to a row line in the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the array control circuit being operable to allow the row activate signal to be applied to a row line in the second array but not to a row line in the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
-
-
44. A computer system, comprising:
-
a processor having a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal prior to generating the plurality of column address bits, the array select signal corresponding to a column address bit and having either a first state or a second state; and
a memory device coupled to the memory controller, the memory device comprising;
a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;
a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and
first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines;
a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal;
a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal;
a mode select circuit generating a mode select signal indicative of operation in either a first or a second mode; and
a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
-
-
56. In a memory device, a method of selecting between first and second arrays of memory cells, the method comprising:
-
determining within the memory device whether the memory device is to operate in either a first mode or a second mode;
receiving a row address, a column address, and an array select signal, the row address and the array select signal being received prior to the column address being received;
opening a row of memory cells in the first and second arrays responsive to determining within the memory device that the memory device is to operate in the first mode;
opening a row of memory cells in the first array but not the second array responsive to receiving an array select signal having a first state after determining within the memory device that the memory device is to operate in the second mode; and
opening a row of memory cells in the second array but not the first array responsive to receiving an array select signal having a second state after determining within the memory device that the memory device is to operate in the second mode. - View Dependent Claims (57, 58, 59, 60, 61)
-
-
62. A method of operating a memory device having first and second memory cell arrays having respective sets of row lines, the method comprising:
-
determining within the memory device whether the memory device is to operate in either a first mode or a second mode;
receiving a row address, a column address, and an array select signal, the row address and the array select signal being received prior to the column address being received;
coupling a row activate signal to respective row lines in the first and second arrays responsive to determining within the memory device that the memory device is to operate in the first mode;
coupling a row activate signal to a row line in the first array but not to a row line in the second array responsive to receiving an array select signal having a first state after determining within the memory device that the memory device is to operate in the second mode; and
coupling a row activate signal to a row line in the second array but not to a row line in the first array responsive to receiving an array select signal having a second state after determining within the memory device that the memory device is to operate in the second mode. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69)
-
Specification