Trench fet with self aligned source and contact

• US 20030085422A1
• Filed: 08/30/2002
• Published: 05/08/2003
• Est. Priority Date: 09/05/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Amali, Adam I., Thapar, Naresh
• Granted Patent: US 7,045,859 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Claims

1. A trench type power MOSgated device comprising a silicon die having an N⁻

drift region and a P type channel formed atop said N⁻

drift region;

a plurality of spaced trenches formed into the top of said die and extending perpendicularly through said P body and into said N⁻

drift region;

each of said trenches having a gate dielectric on the walls thereof and being filled with a conductive polysilicon filler to a height below the top surface of said silicon;

an oxide plug formed atop said each of said polysilicon fillers and filling said trench to at least the top thereof;

spaced N⁺ source diffusion formed into the tops of the walls of said trenches and having a short lateral extension at the tops of each of said trenches and extending for a given depth below the top of said polysilicon fillers; and

a source electrode overlying the top of said silicon and contacting the top surface of said N⁺ source regions and the P channel region between the spaced N⁺ source regions.

2. The device of claim 1 in which said top surface of said silicon and the top surfaces of said oxide plugs are in a substantially common plane.

3. The device of claim 1 wherein said oxide plug is a deposited oxide.

4. The device of claim 1 wherein said gate dielectric is a grown oxide.

5. The device of claim 1 wherein the bottom of each of said trenches is lined with an oxide having a greater thickness than that of said gate dielectric.

6. The device of claim 4 wherein the bottom of each of said trenches is lined with an oxide having a greater thickness than that of said gate dielectric.

7. The device of claim 2 wherein said oxide plug is a deposited oxide.

8. The device of claim 4 wherein said oxide plug is a deposited oxide.

9. The device of claim 5 wherein said oxide plug is a deposited oxide.

10. The device of claim 1 which further includes a termination trench surrounding the active area of said device;

said trench termination being coated with a layer of field oxide, covered in turn by conductive polysilicon, and covered in turn by a deposited oxide.

11. The device of claim 3 which further includes a termination trench surrounding the active area of said device;

said trench termination being coated with a layer of field oxide, covered in turn by conductive polysilicon, and covered in turn by a deposited oxide.

12. The device of claim 5 which further includes a termination trench surrounding the active area of said device;

said trench termination being coated with a layer of field oxide, covered in turn by conductive polysilicon, and covered in turn by a deposited oxide.

13. A trench type MOSgated device;

said trench type device having a vertical trench in a silicon substrate;

said vertical trench having a gate oxide on its vertical walls and being filled with conductive polysilicon to a height below the top of said silicon substrate;

the opening from top of said conductive polysilicon to the top of said substrate being filled with a deposited oxide.