Polishing apparatus and method with belt drive system adapted to extend the lifetime of a refreshing polishing belt provided therein

• US 20030096561A1
• Filed: 11/15/2002
• Published: 05/22/2003
• Est. Priority Date: 12/01/1998
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: ASM NuTool, Inc. (ASM International NV)
• Inventors: Talieh, Homayoun, Ashjaee, Jalai, Young, Douglas, Volodarsky, Konstantin
• Granted Patent: US 6,932,679 B2
• Time in Patent Office: Days
• US Class Current: 451/36
• CPC Class Codes: B24B 21/04 for grinding plane surfaces
• CPC Class Codes: B24B 21/08 Pressure shoes; Pressure members, e.g. backing belts
• CPC Class Codes: B24B 21/22 for producing a reciprocation of the grinding belt normal to its direction of movement
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: B24B 37/04 designed for working plane surfaces
• CPC Class Codes: B24B 37/205 provided with a window for inspecting the surface of the work being lapped
• CPC Class Codes: B24B 47/04 by mechanical gearing only
• CPC Class Codes: B24B 49/16 taking regard of the load

Abstract

The present invention includes a polishing pad or belt secured to a mechanism that allows the pad or belt to move in a reciprocating manner, i.e. in both forward and reverse directions, at high speeds. The constant bidirectional movement of the polishing pad or belt as it polishes the wafer provides superior planarity and uniformity across the wafer surface. When a fresh portion of the pad is required, the pad is moved through a drive system containing rollers, such that the rollers only touch a back side of the pad, thereby minimizing sources of friction other than the wafer that is being polished from the polishing side of the pad, and maximizing the lifetime of the polishing pad.

Claims

1. A method of processing a semiconductor wafer comprising:

positioning the wafer below a wafer housing;

supporting the wafer around its periphery; and

loading the wafer into a wafer housing cavity.

2. The method of claim 1, further comprising extending a support structure proximate to the wafer periphery.

3. The method of claim 1, further comprising retracting a support structure from proximate to the wafer periphery.

4. The method of claim 2, further comprising retracting the support structure from proximate to the wafer periphery.

5. The method of claim 2, further comprising housing the support structure in a movable support structure housing.

6. The method of claim 5, further comprising moving the support structure housing in an upward and downward direction.

8. The method of claim 1, further comprising:

releasing the wafer from the wafer housing cavity;

supporting the wafer around its periphery; and

unloading the wafer from the wafer housing.

9. An integrated circuit manufactured including the method of claim 1.

10. An integrated circuit manufactured including the method of claim 8.

7. The method of claim I, further comprising treating the wafer.

11. A method of processing a semiconductor wafer comprising:

positioning the wafer in a cavity of a wafer housing;

positioning a retractable support structure below the surface of the wafer;

extending the support structure to support the wafer;

moving the support structure so that the wafer is positioned near the surface of the wafer housing; and

clearing the support structure from the surface of the wafer.

12. The method of claim 11, further comprising securing the wafer against the surface of the wafer housing.

13. The method of claim 11, further comprising housing the support structure in a movable support structure housing.

14. The method of claim 13, further comprising moving the support structure housing in an upward and downward direction.

15. The method of claim 11, further comprising aligning the wafer housing with the wafer.

16. The method of claim 11, further comprising treating the wafer.

17. The method of claim 11, further comprising:

positioning the support structure below the surface of the wafer;

extending the support structure to support the wafer; and

moving the support structure so that the wafer is moved away from the surface of the wafer housing.

18. An integrated circuit manufactured including the method of claim 11.

19. A semiconductor wafer processing device comprising:

a wafer housing; and

a support structure attached to the wafer housing configured to load a wafer into a wafer housing cavity.

20. The semiconductor wafer processing device of claim 19, wherein the support structure comprises retractable members.

21. The semiconductor wafer processing device of claim 20, wherein the support structure comprises at least three retractable members.

22. The semiconductor wafer processing device of claim 20, wherein the retractable members are retractable pins.

23. The semiconductor wafer processing device of claim 19, wherein the support structure is further configured to unload the wafer from the wafer housing cavity.

24. The semiconductor wafer processing device of claim 19, further comprising a movable support structure housing configured to house the support structure and to move in an upward and downward direction to load the wafer into the wafer housing cavity.

25. A semiconductor wafer processing device comprising a head assembly having a cavity adapted to support a wafer and a movable pin housing that includes pins adapted to protrude in and out of the pin housing.

26. The semiconductor wafer processing device of claim 25, further comprising a motor configured to move the pin housing in an upward and downward direction.

27. The semiconductor wafer processing device of claim 25, further comprising a vacuum configured to secure the wafer in the cavity.