Apparatus and methods for managing reliability of semiconductor devices

• US 20030097228A1
• Filed: 10/24/2002
• Published: 05/22/2003
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Song, Li, Weiner, Kurt H., Long, Robert Thomas, Satya, Akella V.S.
• Granted Patent: US 6,813,572 B2
• Time in Patent Office: Days
• US Class Current: 702/82
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875

Abstract

Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Claims

1. A method of determining whether to perform burn-in a semiconductor product, comprising:

for the semiconductor product, determining a time to fail for one or more failure mechanisms;

for the semiconductor product, determining an instantaneous failure rate for the one or more failure mechanisms based on the determined time to fail for the one or more failure mechanisms and yield information obtained from the semiconductor product;

invoking a burn-in procedure on the semiconductor product when the determined instantaneous failure rate for such semiconductor product is not within a predetermined specification bound; and

skipping the burn-in procedure when the determined instantaneous failure rate for such semiconductor product is within the predetermined specification bound.

2. A method as recited in claim 1, wherein the semiconductor product is a semiconductor product wafer.

3. A method as recited in claim 1, wherein the semiconductor product is a semiconductor product wafer lot.

4. A method as recited in claim 1, wherein the determination of the instantaneous failure rate is based indirectly on the yield information and such determination comprises:

for the semiconductor product, determining a critical area for reliability failure;

inspecting one or more test structures on the semiconductor product to determine yield information for the semiconductor product lot immediately after fabrication;

determining a reliability fault density for reliability defects in the semiconductor product based on the determined yield information and the determined critical area for reliability failure; and

for the semiconductor product, determining an instantaneous failure rate for the one or more failure mechanisms based on the determined time to failure for the one or more failure mechanisms.

5. A method as recited in claim 4, wherein determining the critical area for reliability failure comprises:

determining a probability of failure function for yield of the semiconductor product;

providing a defect size distribution for the semiconductor product;

determining a critical area for yield for the semiconductor product based on the determined probability of failure function for yield and the defect size distribution for the semiconductor product;

determining a probability of failure function for yield plus reliability;

determining a critical area for yield plus reliability from the probability of failure function for yield plus reliability; and

determining the critical area for reliability by subtracting the critical area for yield from the critical yield for yield plus reliability.

6. A method as recited in claim 5, wherein the determination of the probability of fail function for yield plus reliability comprises shifting a curve of the probability of fail function for yield as a function of defect size to a reliability defect size that will cause a reliability fault.

7. A method as recited in claim 4, wherein inspecting one or more test structures on the semiconductor product to determine yield information for the semiconductor product lot immediately after fabrication comprises:

inspecting the one or more test structures to determine test structure yield;

determining a log of test structure yield as a function of a size of the one or more test structures; and

determining a defect density, systematic yield, and a alpha curvature or defect cluster parameter from the log of test structure yield as a function of the size.

8. A method as recited in claim 1, wherein the one or more failure mechanisms are selected from a group consisting of electromigration, gate oxide breakdown, and hot carrier injection.

9. A computer program product for determining whether to perform burn-in a semiconductor product, the computer program product comprising:

at least one computer readable medium;

computer program instructions stored within the at least one computer readable product configured to;

for the semiconductor product, determine a time to fail for one or more failure mechanisms;

for the semiconductor product, determine an instantaneous failure rate for the one or more failure mechanisms based on the determined time to fail for the one or more failure mechanisms and yield information obtained from the semiconductor product;

determine to perform a burn-in procedure on the semiconductor product when the determined instantaneous failure rate for such semiconductor product is not within a predetermined specification bound; and

determine to skip the burn-in procedure when the determined instantaneous failure rate for such semiconductor product is within the predetermined specification bound.

10. A computer program product as recited in claim 9, wherein the determination of the instantaneous failure rate is based indirectly on the yield information and such determination comprises:

for the semiconductor product, determining a critical area for reliability failure;

providing yield results from inspecting one or more test structures on the semiconductor product and using the yield results to determine yield information for the semiconductor product lot immediately after fabrication;

determining a reliability fault density for reliability defects in the semiconductor product based on the determined yield information and the determined critical area for reliability failure; and

for the semiconductor product, determining an instantaneous failure rate for the one or more failure mechanisms based on the determined time to failure for the one or more failure mechanisms.

11. A computer program product as recited in claim 10, wherein determining the critical area for reliability failure comprises:

determining a probability of failure function for yield of the semiconductor product;

providing a defect size distribution for the semiconductor product;

determining a critical area for yield for the semiconductor product based on the determined probability of failure function for yield and the defect size distribution for the semiconductor product;

determining a probability of failure function for yield plus reliability;

determining a critical area for yield plus reliability from the probability of failure function for yield plus reliability; and

determining the critical area for reliability by subtracting the critical area for yield from the critical yield for yield plus reliability.

12. A computer program product as recited in claim 11, wherein the determination of the probability of fail function for yield plus reliability comprises shifting a curve of the probability of fail function for yield as a function of defect size to a reliability defect size that will cause a reliability fault.

13. A computer system for determining whether to perform burn-in on such semiconductor product, the system comprising a processor and at least one memory operable to:

for the semiconductor product, determine a time to fail for one or more failure mechanisms;

for the semiconductor product, determine an instantaneous failure rate for the one or more failure mechanisms based on the determined time to fail for the one or more failure mechanisms and yield information provided from inspection of such semiconductor product;

determine to perform a burn-in procedure on the semiconductor product when the determined instantaneous failure rate for such semiconductor product is within a predetermined specification; and

determine to skip the burn-in procedure when the determined instantaneous failure rate for such semiconductor product is not within the predetermined specification

14. A computer system as recited in claim 13, wherein the determination of the instantaneous failure rate is based indirectly on the yield information and such determination comprises:

for the semiconductor product, determining a critical area for reliability failure;

providing yield results from inspecting one or more test structures on the semiconductor product and using the yield results to determine yield information for the semiconductor product lot immediately after fabrication;

determining a reliability fault density for reliability defects in the semiconductor product based on the determined yield information and the determined critical area for reliability failure; and

for the semiconductor product, determining an instantaneous failure rate for the one or more failure mechanisms based on the determined time to failure for the one or more failure mechanisms.

15. A computer system as recited in claim 14, wherein determining the critical area for reliability failure comprises:

determining a probability of failure function for yield of the semiconductor product;

providing a defect size distribution for the semiconductor product;

determining a critical area for yield for the semiconductor product based on the determined probability of failure function for yield and the defect size distribution for the semiconductor product;

determining a probability of failure function for yield plus reliability;

determining a critical area for yield plus reliability from the probability of failure function for yield plus reliability; and

determining the critical area for reliability by subtracting the critical area for yield from the critical yield for yield plus reliability.

16. A computer system as recited in claim 15, wherein the determination of the probability of fail function for yield plus reliability comprises shifting a curve of the probability of fail function for yield as a function of defect size to a minimum reliability defect size that will cause a reliability fault.

17. A method of determining whether to perform burn-in testing on at least a part of an integrated circuit product, the product having a plurality of associated test structures, the method comprising:

determining a yield for the test structures;

determining a measure of vulnerability to processing defects of a design of at least one portion of the product;

determining a particular defect density based on a particular test structure; and

based on the yield, the measure of vulnerability and the particular defect density, determining whether to perform burn-in testing on the product.

18. A method as recited in claim 17, wherein the product is in the form of a plurality of wafers processed on a processing line, and each wafer comprised in the set of wafers has a test structure.

19. A method as recited in claim 18, wherein the measure of vulnerability to processing defects is a critical area.

20. A method as recited in claim 18, wherein the processing line is a fabrication semiconductor production line.

21. A method as recited in claim 17, wherein the product is in the form of multiple products on a particular wafer, the method further comprising applying the determination as to whether to perform burn-in is applied to all products.

22. A method as recited in claim 18, wherein all test structures comprised in the set of wafers are substantially identical with the particular test structure.

23. A method as recited in claim 18, wherein the set of wafers comprises all wafers processed on the processing line.

24. A method as recited in claim 18, wherein the set of wafers comprises less than all wafers processed on the processing line.

25. A method as recited in claim 18, wherein the yield represents a percentage of test structures comprised in the set of wafers that exhibit less than a certain number of defects.

26. A method as recited in claim 18, wherein the yield represents the percentage of test structures comprised in the set of wafers that exhibit no defects.

27. A method as recited in claim 18, further comprising determining a set of yield parameters, such as a systematic yield and a defect cluster factor, based on the yield, wherein determining whether to perform burn-in testing on the product is based on the yield parameters.

28. A method as recited in claim 19, wherein the critical area is based on a single defect mechanism.

29. A method as recited in claim 28, wherein the defect mechanism is a partial or complete electrical short.

30. A method as recited in claim 28, wherein the defect mechanism is a partial or complete electrical open.

31. A method as recited in claim 18, further comprising determining a defect density for the wafers based on the global yield figure and on the measure of vulnerability.