Wideband regulator with fast transient suppression circuitry

• US 20030098674A1
• Filed: 01/08/2003
• Published: 05/29/2003
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Primarion Incorporated (Infineon Technologies AG)
• Inventors: Ostrom, Kenneth A.
• Granted Patent: US 6,661,212 B2
• Time in Patent Office: Days
• US Class Current: 323/276
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A wideband voltage regulator is configured to provide suppression of fast transients, which can include a boosting circuit and a sensing circuit. The boosting circuit can be suitably configured to boost the voltage regulator response, while the sensing circuit can determine when such a boost may be desired. Accordingly, the response of the voltage regulator can be accelerated to a fast load transient beyond the closed loop bandwidth limited response or the slew rate limited response of the voltage regulator. An exemplary voltage regulator can be configured with an active sensing circuit comprising a sensing amplifier with switch control outputs, and a boosting circuit comprising N stored charge sources, e.g.; boost capacitors, and (3N−1) switches that are configured to accelerate the voltage regulators response to a fast load transient beyond the closed loop bandwidth limited or slew rate limited response of the voltage regulator.

Claims

1. A voltage regulator configured for providing for the suppression of current transients, said voltage regulator comprising:

a closed loop amplifier for determining a difference between a reference voltage and an output voltage;

a compensation capacitor coupled to said closed loop amplifier;

an output buffer amplifier coupled to said compensation capacitor, said output buffer amplifier being configured to provide an output for said voltage regulator comprising the output voltage;

a boosting circuit coupled to said closed loop amplifier and said compensation capacitor and being configured for providing a boosted voltage charge, said boosting circuit comprising at least one stored charge source and at least two switching devices; and

a sensing circuit configured for sensing a load transient event to permit said boosted voltage charge to be provided to an input of said output buffer amplifier, said sensing circuit comprising a threshold voltage and a control device for controlling operation of said at least two switching devices, and

wherein said sensing circuit operates said at least two switching devices based on occurrence of the load transient event such that an accelerated response of said voltage regulator to a fast load transient beyond at least one of a closed loop bandwidth limited response and a slew rate limited response of said voltage regulator can be realized.

2. The voltage regulator according to claim 1, wherein said load transient event occurs when the output voltage falls below a difference between the output voltage and a threshold voltage.

3. The voltage regulator according to claim 1, wherein said boosting circuit comprises at least one boosting capacitor.

4. The voltage regulator according to claim 1, wherein said boosting circuit comprises N stored charge sources and 3N−

1 switching devices.

5. The voltage regulator according to claim 1, wherein said sensing circuit is configured for facilitating the providing of said boosted voltage charge to said output buffer amplifier by comparing the output voltage of said output buffer amplifier to the reference voltage.

6. The voltage regulator according to claim 5, wherein said sensing circuit is triggered on a one-shot basis to provide said boosted voltage charge to said output buffer amplifier through operation of said at least two switching devices.

7. The voltage regulator according to claim 6, wherein operation of said at least two switching devices is reset after a predetermined time interval.

8. The voltage regulator according to claim 6, wherein operation of said at least two switching devices is reset after determining that the output voltage has been boosted to a desired level.

9. The voltage regulator according to claim 6, wherein operation of said at least two switching devices is reset after a preselected pulse width.

10. The voltage regulator according to claim 1, wherein said sensing circuit is configured for facilitating the providing of said boosted voltage charge to said output buffer amplifier by comparing a voltage drop across a parasitic inductance, said parasitic inductance being configured between the output of said voltage regulator and a load device, to the reference voltage.

11. The voltage regulator according to claim 10, wherein said sensing circuit is triggered on a one-shot basis to provide said boosted voltage charge to said output buffer amplifier through operation of said at least two switching devices.

12. The voltage regulator according to claim 11, wherein operation of said at least two switching devices is reset after a predetermined time interval.

13. The voltage regulator according to claim 11, wherein operation of said at least two switching devices is reset after determining that the output voltage has been boosted to a desired level.

14. The voltage regulator according to claim 11, wherein operation of said at least two switching devices is reset after a preselected pulse width.

15. The voltage regulator according to claim 1, wherein said sensing circuit is configured for facilitating the providing of said boosted voltage charge to said output buffer amplifier by comparing a difference between a voltage drop across a parasitic inductance of a supply side of a load device and a parasitic inductance of a ground side of the load device.

16. The voltage regulator according to claim 1, wherein a differential offset voltage is added to a sensed difference voltage to provide a sensitivity setting of said sensing circuit.

17. An integrated circuit configured for the suppression of current transients occurring within said integrated circuit, said integrated circuit comprising:

an input power supply terminal for receiving an input power supply;

a reference voltage terminal for receiving a reference voltage; and

a voltage regulator coupled to said input power supply terminal and said reference voltage terminal and configured for providing an output voltage, said voltage regulator comprising;

a closed loop amplifier configured for minimizing a difference in voltage between the reference voltage and the output voltage;

a compensation capacitor coupled to said closed loop amplifier;

an output buffer amplifier having an input terminal coupled to said compensation capacitor, said output buffer amplifier having an output terminal coupled to the output voltage of said voltage regulator;

a boosting circuit coupled to said closed loop amplifier and said compensation capacitor and being configured for providing a boosted voltage charge, said boosting circuit comprising at least one stored charge source and at least two switching devices; and

a sensing circuit comprising a threshold voltage and a control device for controlling operation of said at least two switching devices, said sensing circuit being configured for providing an accelerated response of said voltage regulator by permitting said boosted voltage charge to be provided to an input of said output buffer amplifier upon determination that the output voltage falls below said threshold voltage.

18. The integrated circuit according to claim 17, wherein said boosting circuit is configured with said at least two switching devices to be connected between a bias voltage and ground during a charging phase and to be connected in parallel with said compensation capacitor during a boosting phase.

19. The integrated circuit according to claim 17, wherein said boosting circuit comprises at least one boosting capacitor.

20. The integrated circuit according to claim 18, wherein said boosting circuit comprises N boost capacitors and 3N−

1 switching devices.

21. The integrated circuit according to claim 19, wherein said N boost capacitors comprise a total capacitance between 1 pF and 100 nF, said total capacitance being scaled based on a load device coupled to said voltage regulator.

22. The integrated circuit according to claim 17, wherein said sensing circuit is configured for switching said boosted voltage charge to said output buffer amplifier by comparing the output voltage to the reference voltage.

23. The integrated circuit according to claim 17, wherein said sensing circuit is triggered on a one-shot basis to provide said boosted voltage charge to said output buffer amplifier through operation of said at least two switching devices.

24. The voltage regulator according to claim 17, wherein operation of said at least two switching devices is reset after occurrence of at least one of a determination that the output voltage has been boosted to a desired level, after a predetermined time interval and after a preselected width pulse.

25. The integrated circuit according to claim 17, wherein said sensing circuit is configured for facilitating the providing of said boosted voltage charge to said output buffer amplifier by comparing a voltage drop across a parasitic inductance to the reference voltage, said parasitic inductance being configured between the output of said voltage regulator and a load device.

26. The integrated circuit according to claim 17, wherein said sensing circuit is configured for facilitating the providing of said boosted voltage charge to said output buffer amplifier by comparing a difference between a voltage drop across a parasitic inductance of a supply side of a load device and a parasitic inductance of a ground side of the load device.

27. The integrated circuit according to claim 17, wherein a differential offset voltage is added to a sensed difference voltage to provide a sensitivity setting of said sensing circuit.

28. A method for suppressing current transients in a voltage regulator, said method comprising the steps of:

determining a voltage difference between a reference voltage and an output voltage in said voltage regulator;

minimizing said voltage difference between the reference voltage and the output voltage with a closed loop amplifier through use of a compensation capacitor;

charging a stored charge source in a boosting circuit to provide a boosted charge voltage, said boosting capacitor coupled between a bias voltage and ground;

determining when the output voltage falls below a difference between the reference voltage and a threshold voltage through use of a sensing circuit; and

boosting the output voltage through operation of said sensing circuit until a desired voltage level is obtained.

29. The method according to claim 28, wherein said boosting circuit comprises at least one boosting capacitor.

30. The method according to claim 28, wherein said boosting circuit comprises N boost capacitors and 3N−

1 switching devices, and said step of charging comprises closing at least one of said 3N−

1 switching devices such that said boosting capacitor is coupled between a bias voltage and ground.

31. The method according to claim 28, wherein said step of determining when the output voltage falls below a threshold voltage comprises comparing with said sensing circuit the output voltage with the reference voltage.

32. The method according to claim 28, wherein said step of determining when the output voltage falls below a threshold voltage comprises comparing with said sensing circuit a voltage drop across a parasitic inductance to the reference voltage, said parasitic inductance being configured between an output of said voltage regulator and a load device.

33. The method according to claim 28, wherein said step of determining when the output voltage falls below a threshold voltage comprises comparing with said sensing circuit a difference between a voltage drop across a parasitic inductance of a supply side of a load device and a parasitic inductance of a ground side of the load device.

34. The method according to claim 28, wherein said step of boosting the output voltage through operation of said sensing circuit comprises triggering said boosted circuit on a one-shot basis to provide said boosted voltage charge to the output voltage.

35. The method according to claim 28, further comprising the step of adding differential offset voltage to a sensed difference voltage to provide a sensitivity setting of said sensing circuit.

36. The method according to claim 28, further comprising the step of resetting said at least two switching devices after occurrence of at least one of a determination that the output voltage has been boosted to a desired level, after a predetermined time interval and after a preselected width pulse.