SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20030100152A1
• Filed: 09/16/1994
• Published: 05/29/2003
• Est. Priority Date: 09/20/1993
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SUGAWARA, AKIRA, OHNUMA, HIDETO, UOCHI, HIDEKI, SUZAWA, HIDEOMI, TAKEMURA, YASUHIKO, ZHANG, HONGYONG, KONUMA, TOSHIMITSU, YAMAGUCHI, NAOAKI, SUZUKI, ATSUNORI, UEHARA, YUKIKO
• Granted Patent: US 6,867,431 B2
• Time in Patent Office: Days
• US Class Current: 438/164
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 21/31687 by anodic oxidation
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD

Abstract

A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode comprising an anodizable material on a gate insulating film;

forming a first anodic oxide film by applying an electric current to said gate electrode in a first electrolyte; and

forming a second anodic oxide film between said gate electrode and said first anodic oxide film by applying an electric current to said gate electrode in a second electrolyte,

wherein said first anodic oxide film is relatively porous as compared with said second anodic oxide film.

2. The method of claim 1 wherein said first electrolyte has a higher acidness than said second electrolyte.

3. The method of claim 2 wherein said second electrolyte is neutral.

4. The method of claim 1 wherein said first electrolyte is an acid aqueous solution containing a material selected from the group consisting of citric acid, oxalic acid, phosphoric acid, chromic acid, and sulfuric acid.

5. The method of claim 1 wherein said second electrolyte is an ethylene glycol solution containing a tartaric acid, boric acid or nitric acid.

6. The method of claim 1 wherein said first electrolyte has a pH lower than 2.0 while said second electrolyte has a pH higher than 2.0.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming a semiconductor film on an insulating surface;

forming an insulating film on said semiconductor film;

forming a gate electrode on said insulating film;

first anodizing said gate electrode to form a first anodic oxide film on at least a side surface of said gate electrode;

removing or thinning a portion of said insulating film by etching with said first anodic oxide film used as a mask to form a gate insulating film;

removing said first anodic oxide film; and

introducing one conductivity impurity into said semiconductor film with said gate electrode used as a mask and through a portion of said gate insulating film.

8. The method of claim 7 further comprising the step of second anodizing said gate electrode to form a second anodic oxide film after said first anodizing step.

9. The method of claim 7 further comprising activating said impurity after said introducing step by irradiating light thereon.

10. A method for manufacturing a semiconductor device comprising the steps of:

forming an active silicon semiconductor layer on an insulating surface;

forming an insulating film on said active semiconductor layer;

forming a gate electrode on said insulating film;

anodizing a surface of said gate electrode in an electrolyte to form a first anodic oxide film thereon;

removing a portion of said insulating film by etching with said first anodic oxide film used as a mask in order to expose a surface of said active semiconductor layer and to form a gate insulating film;

coating a metal film capable of forming a silicide on at least on said exposed surface of said active semiconductor layer; and

reacting said metal film and said active semiconductor layer to form silicide regions in said active semiconductor layer.

11. The method of claim 10 further comprising the step of second anodizing said gate electrode to form a second anodic oxide film after said first anodizing step.

12. The method of claim 10 wherein said metal film is reacted with said active semiconductor layer by irradiating a laser or a light equivalent to the laser.

13. The method of claim 10 further comprising the step of introducing one conductivity impurity into a portion of said active semiconductor layer after said reacting step in order to form a pair of first impurity regions an a pair of second impurity regions containing said impurity at a higher concentration than said first impurity regions.

14. The method of claim 13 further comprising the step of removing a portion of said gate insulating film after said introducing step.

15. A method for manufacturing a semiconductor device comprising the steps of:

forming an active silicon semiconductor layer on an insulating surface;

forming a insulating film on said active semiconductor layer;

forming a conductive material for forming a gate electrode on said insulating film;

forming a mask on a selected portion of said conductive material;

patterning said conductive material in accordance with said mask to form a gate electrode;

forming a first anodic oxide film on a side surface of said gate electrode while said mask covers an upper portion of said gate electrode;

removing or thinning a portion of said insulating film with said first anodic oxide film used as a mask to form a gate insulating film;

removing said first anodic oxide film; and

introducing one conductivity impurity into said semiconductor layer with said gate electrode used as a mask and through a portion of said gate insulating film.

16. The method of claim 15 further comprising the step of forming a second anodic oxide film after the formation of said first anodic oxide film.

17. The method of claim 15 further comprising activating said impurity after said introducing step by irradiating light thereon.

18. The method of claim 16 wherein said second anodic oxide film is formed before said removing or thinning step.

19. The method of claim 16 wherein said second anodic oxide film is formed after said removing or thinning step.

20. A method for manufacturing a semiconductor device comprising the steps of:

forming an active silicon semiconductor layer on an insulating surface;

forming a insulating film on said active semiconductor layer;

forming a conductive material for forming a gate electrode on said insulating film;

forming a mask on a selected portion of said conductive material;

patterning said conductive material in accordance with said mask to form a gate electrode;

forming a first anodic oxide film on a side surface of said gate electrode while said mask covers an upper portion of said gate electrode;

removing a portion of said gate insulating film with said first anodic oxide film used as a mask to form a gate insulating film and to expose a surface of said semiconductor layer;

coating a metal film capable of forming a silicide on at least on said exposed surface of said active semiconductor layer; and

reacting/said metal film and said active semiconductor layer to form silicide regions in said active semiconductor layer.

21. The method of claim 20 further comprising the step of second anodizing said gate electrode to form a second anodic oxide film after said first anodizing step.

22. The method of claim 20 wherein said metal film is reacted with said active semiconductor layer by irradiating a laser or a light equivalent to the laser.

23. The method of claim 20 further comprising the step of introducing one conductivity impurity into a portion of said active semiconductor layer after said reacting step in order to form a pair of first impurity regions and a pair of second impurity regions containing said impurity at a higher concern than said first impurity regions.

24. The method of claim 23 further comprising the step of removing a portion of said gate insulating after said introducing step.

25. The method of claim 21 wherein said second anodic oxide film is formed before said removing step.

26. The method of claim 21 wherein said second anodic oxide film is formed after said removing step.

27. A method for manufacturing a semiconductor device comprising:

forming an electrode comprising an anodizable material on a surface;

forming a mask on an upper surface of said electrode; and

anodically oxidize said electrode in an electrolyte to form an oxide film on a side surface of said electrode,

wherein said mask comprises an anodic oxide layer of said electrode formed on said upper surface in contact therewith and an organic material formed on said anodic oxide.

28. A thin film transistor comprising:

an insulating surface;

a channel semiconductor layer formed on said insulating surface;

a pair of first impurity regions formed on said insulating surface, between which said channel semiconductor layer extends;

a pair of second impurity regions having a lower resistivity than said first impurity regions, located adjacent to aid first impurity regions; and

a gate electrode formed over said channel semiconductor layer with a gate insulating film interposed therebetween,

wherein said gate insulating film extends beyond edges of said channel semiconductor layer, and a boundary between said first impurity regions and second impurity regions is approximately coextensive with edges of said gate insulating film.

29. The thin film transistor of claim 28 wherein said second impurity regions comprise a metal silicide.

30. The thin film transistor of claim 28 further comprising an anodic oxide on a surface of said gate electrode formed by anodic oxidizing the gate electrode.

31. The thin film transistor of claim 29 wherein said metal silicide contains a metal selected from the group consisting of titanium, nickel, molybdenum, tungsten, platinum and paradium.

32. A thin film transistor comprising:

an insulating surface;

a channel semiconductor layer formed on said insulating surface;

a pair of first impurity regions formed on said insulating surface, between which said channel semiconductor layer extends;

a pair of second impurity regions having a lower resistivity than said first impurity regions, located adjacent to said first impurity regions; and

a gate electrode formed over said channel semiconductor layer with a gate insulating film interposed therebetween,

wherein said gate insulating film does not cover said second impurity regions and said second impurity regions comprise a metal silicide.

33. The transistor of claim 32 wherein said silicide contains a metal selected from the group consisting of titanium and nickel.