Method of depositing a low dielectric with organo silane

• US 20030113992A1
• Filed: 11/21/2002
• Published: 06/19/2003
• Est. Priority Date: 02/11/1998
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Cheung, David, Jeng, Shin-Puu, Yau, Wai-Fan, Liu, Kuowei, Yu, Yung-Cheng
• Granted Patent: US 6,770,556 B2
• Time in Patent Office: Days
• US Class Current: 438/623
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH₃SiH₃, and N₂O.

Claims

1. A process for depositing an intermetal dielectric layer on a semiconductor substrate, comprising reacting one or more silicon compounds with an oxidizing gas while applying RF power to deposit the low dielectric constant film on the semiconductor substrate, wherein each silicon compound comprises the structure:

2. The process of claim 1, wherein the oxidizing gas comprises oxygen.

3. The method of claim 1, wherein the RF power is provided by a mixed frequency power source.

4. The method of claim 3, wherein the mixed frequency power source provides RF power at a high frequency of about 13.56 MHz and a low frequency of about 360 KHz to about 1 MHz.

5. The method of claim 1, wherein the oxidizing gas comprises N₂O.

6. The method of claim 1, wherein the intermetal dielectric layer is annealed.

7. The method of claim 1, wherein a dielectric material is deposited on the intermetal dielectric layer.

8. The method of claim 1, wherein the one or more silicon compounds comprises methylsilane.

9. A process for depositing an interconnect on a semiconductor substrate, comprising:

depositing a dielectric layer by reacting a silicon compound with an oxidizing gas while applying RF power, wherein the silicon compound comprises the structure;

and wherein the film retains sufficient silicon-carbon bonds to have a dielectric constant of about 3 or less;

etching at least one opening in the dielectric layer; and

depositing a conductive material in the opening.

10. The process of claim 9, wherein the conductive material is copper.

11. The method of claim 9, wherein the oxidizing gas comprises O₂ or N₂O.

12. The method of claim 10, wherein the compound is methylsilane.

13. The method of claim 9, wherein the dielectric layer is annealed.

14. The method of claim 9, wherein a dielectric material is deposited on the dielectric layer prior to the etching.

15. A process for depositing an interconnect on a semiconductor substrate, comprising:

depositing a conformal lining layer on a patterned metal layer from process gases comprising one or more silicon compounds and an oxidizing gas while applying RF power, wherein at least one of the silicon compounds comprises the structure;

and wherein the conformal lining layer retains sufficient silicon-carbon bonds to have a dielectric constant of about 3 or less; and

depositing a gap filling layer on the conformal lining layer.

16. The process of claim 15, wherein the gap filling layer is deposited by reaction of methylsilane and hydrogen peroxide.

17. The method of claim 15, wherein the oxidizing gas comprises O₂.

18. The method of claim 15, wherein the conformal lining layer is annealed.

19. The method of claim 15, wherein the oxidizing gas comprises N₂O.

20. The method of claim 15, wherein the RF power is provided by a mixed frequency power source.