Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter

• US 20030126322A1
• Filed: 02/27/2003
• Published: 07/03/2003
• Est. Priority Date: 06/09/1999
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Micalizzi, Charles Jr., Sippy, Chandru M., Konda, Dharma R.
• Granted Patent: US 6,810,440 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Claims

1. A method of automatically loading I/O command blocks from a host system into a command block buffer that is used by a processor on a host adapter to store I/O command blocks to be processed, the method comprising:

monitoring a request queue to determine when a new command is in the request queue;

determining the address of said new command in said request queue;

retrieving a buffer address identified from a list of available buffer locations;

transferring the data from said new command address to said buffer address; and

writing said buffer address to a list of filled buffer locations.

2. The method of claim 1, wherein the monitoring of said request queue comprises using at least one register on the host adapter to send information between the host system and the host adapter.

3. The method of claim 1, wherein the transfer of data from the new command address to the buffer address is a direct memory access (DMA) transfer operation.

4. The method of claim 1, wherein the host adapter is a Fibre Channel host adapter.

5. The method of claim 1, wherein the host system and the host adapter are coupled together by a peripheral component interconnect (PCI) bus.

6. A circuit for accelerating the processing of I/O commands from a host system to a host adapter, the circuit comprising:

a host adapter RAM;

a monitoring unit to monitor a request queue in host memory, wherein the monitoring unit generates a signal in response to a detection of I/O requests;

a data retrieval unit responsive to said monitoring unit, wherein said data retrieval unit transfers data from a location in said request queue containing an I/O request to a buffer on the host adapter RAM, wherein the buffer address is read from an available list in the host adapter RAM, and wherein said data retrieval unit writes said buffer address to a filled buffer list in the host adapter RAM; and

a processor to read said I/O command from said buffer, said buffer address being read from said filled buffer list, wherein said processor writes said buffer address to said available buffer list after processing said I/O command.

7. The circuit of claim 6, wherein the monitoring unit comprises at least one register on the host adapter which is used to send information between the host system and the host adapter.

8. The circuit of claim 6, wherein the data retrieval unit transfers data from the request queue to the host adapter RAM by setting up a direct memory access (DMA) operation.

9. The circuit of claim 6, wherein the host adapter is a Fibre Channel host adapter.

10. The circuit of claim 6, wherein the host system and the host adapter are coupled together by a peripheral component interconnect (PCI) bus.

11. The circuit of claim 6, wherein the monitoring unit and data retrieval unit comprise a single processor which executes instructions from the adapter RAM.

12. A method of automatically transferring I/O status blocks from a host adapter to a host system, the method comprising:

monitoring a filled buffer list in adapter RAM, said list identifying buffers in adapter RAM containing I/O status blocks;

determining the buffer address where an I/O status block is stored from an entry in the filled buffer list;

transferring said I/O status block from said adapter RAM to a response queue in host memory; and

writing said buffer address to a free buffer location list in adapter RAM.

13. A circuit for automatically transferring I/O status blocks from a host adapter to a host system, the circuit comprising:

a host adapter RAM;

a monitoring unit to monitor a filled buffer list in adapter RAM, wherein the monitoring unit generates a signal in response to a detection of a new entry to the filled buffer list;

a data retrieval unit responsive to said monitoring unit, wherein said data retrieval unit transfers data from a buffer in said host adapter RAM which is identified by an entry in the filled buffer list to a response queue in the host system, and wherein the buffer address is read from a filled list in the host adapter RAM, and wherein said data retrieval unit writes said buffer address to a free buffer list in the host adapter RAM; and

a processor to write said I/O status block to said buffer, said buffer address being read from said free buffer list, wherein said processor writes said buffer address to said filled buffer list after writing said I/O status block.