Method and user interface for debugging an electronic system

• US 20030131325A1
• Filed: 07/31/2002
• Published: 07/10/2003
• Est. Priority Date: 11/30/1999
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Bridges2Silicon, Inc.
• Inventors: Beardslee, John Mark, Schubert, Nils Endric, Koch, Gernot Heinrich, Poeppe, Olaf
• Granted Patent: US 6,823,497 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Claims

11. A graphical user interface for instrumenting or debugging an electronic system design, said graphical user interface comprising:

a hardware description language (HDL) code pane that displays HDL code describing the electronic system design; and

a design navigation pane that displays a navigable, hierarchical description of the electronic system design.

1. A method for facilitating debugging of a fabricated integrated circuit, said method comprising:

(a) receiving a high level hardware description language (HDL) description or a representation derived therefrom for electronic circuitry to be produced within the fabricated integrated circuit;

(b) displaying the high level HDL description for the electronic circuitry on a display device associated with a user;

(c) determining aspects of the electronic circuitry to be examined or modified during debugging of the fabricated integrated circuit, said determining (c) operates to determine the aspects of the electronic circuitry through selections made with respect to the high level HDL description for the electronic circuitry;

(d) displaying, on the display device, a visual indication of the selections that have been made with respect to the high level HDL description for the electronic circuitry;

(e) determining design instrumentation circuitry based on the aspects of the electronic circuitry determined to be examined or modified; and

(f) incorporating the design instrumentation circuitry into the electronic circuitry, thereby facilitating debugging of the fabricated integrated circuit.

2. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made automatically without user interaction.

3. A method as recited in claim 1, wherein the selections are automatically made by an instrumentor.

4. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made through user interaction with a command line interface.

5. A method as recited in claim 1, wherein the selections made with respect to the high level HDL description are made either interactively or in batch mode at various levels of granularity.

6. A method as recited in claim 1, wherein said displaying (d) of the visual indication of the selections that have been made displays tags with the high level HDL description for the electronic circuitry being displayed by said displaying (b).

7. A method as recited in claim 1, wherein said determining (c) permits alteration of the design instrumentation circuitry to tradeoff debugging coverage versus area cost.

8. A method as recited in claim 7, wherein said method further comprises:

displaying the area cost on the display device during or after said determining (c).

9. A method as recited in claim 7, wherein the cost area is dependent on a target technology for the electronic circuitry.

10. A method as recited in claim 7, wherein the cost area is with respect to one of FPGA slices, PLD logic elements, or ASIC gate equivalents.

12. A graphical user interface as recited in claim 11, wherein the navigable, hierarchical description is displayed in said design navigation pane in a tree-like structure.

13. A graphical user interface as recited in claim 11, wherein visual indicators are displayed in said HDL code pane interrelated with the HDL code.

14. A graphical user interface as recited in claim 13, wherein at least one of the visual indicators indicates the status of at least one of a break-point and a watch-point.

15. A graphical user interface as recited in claim 13, wherein at least one of the visual indicators indicates the status of at least one of design visibility and design patching.

16. A graphical user interface as recited in claim 13, wherein the visual indicators indicate selections with respect to the HDL code being displayed in said HDL code pane.

17. A graphical user interface as recited in claim 16, wherein said graphical user interface further comprises:

a status pane that displays status information pertaining to at least the selections.

18. A graphical user interface as recited in claim 17, wherein said graphical user interface further comprises:

a command line interface pane capable of receiving a command input thereto.

19. A graphical user interface as recited in claim 17, wherein said status pane and said command line interface share a common pane.

20. A graphical user interface as recited in claim 11, wherein said graphical user interface further comprises:

a status and command line pane that displays status information pertaining to at least the selections and that of receiving a command input.

25. A computer readable medium as recited in claim 21, wherein said computer program code for displaying of the visual indication of the selections that have been made displays tags with the high level HDL description for the electronic circuitry.

26. A computer readable medium as recited in claim 21, wherein said computer program code for determining the aspects of the electronic circuitry permits alteration of the design instrumentation circuitry to tradeoff debugging coverage versus area cost.

27. A computer readable medium as recited in claim 26, wherein said computer readable medium further comprises:

computer program code for displaying the area cost on the display device.

28. A computer readable medium as recited in claim 26, wherein the cost area is dependent on a target technology for the electronic circuitry.

21. A computer readable medium that includes at least computer program code for facilitating debugging of a fabricated integrated circuit, said computer readable medium comprising:

computer program code for receiving a high level hardware description language (HDL) description or a representation derived therefrom for electronic circuitry to be produced within the fabricated integrated circuit;

computer program code for displaying the high level HDL description for the electronic circuitry associated with a user;

computer program code for determining aspects of the electronic circuitry to be examined or modified during debugging of the fabricated integrated circuit, the aspects of the electronic circuitry being determined through selections made with respect to the high level HDL description for the electronic circuitry;

computer program code for displaying a visual indication of the selections that have been made with respect to the high level HDL description for the electronic circuitry;

computer program code for determining design instrumentation circuitry based on the aspects of the electronic circuitry determined to be examined or modified; and

computer program code for incorporating the design instrumentation circuitry into the electronic circuitry, thereby facilitating debugging of the fabricated integrated circuit.

22. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made automatically without user interaction.

23. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made through user interaction with a command line interface.

24. A computer readable medium as recited in claim 21, wherein the selections made with respect to the high level HDL description are made either interactively or in batch mode at various levels of granularity.

25-1. A computer readable medium as recited in claim 16, wherein said method further comprising:

computer program code for displaying the high-level HDL description with the HDL-related debug information related thereto.

26-2. A computer readable medium as recited in claim 25, wherein said computer program code for displaying operates to display the HDL-related debug information as visual indicators on the HDL-related debug information being displayed.

27-3. A computer readable medium as recited in claim 26, wherein the visual indicators are tags.