Hierarchical test circuit structure for chips with multiple circuit blocks
First Claim
1. A hierarchical test control network for a chip design, comprising:
- a plurality of test control circuit blocks in a hierarchical structure having a plurality of hierarchical levels, said test control circuit blocks comprising a top-level test control circuit block having a chip access port (CAP) controller; and
a plurality of lower-level test control circuit blocks, one or more of said lower-level test control circuit blocks at each of said hierarchical levels, at least one of said lower-level test control circuit blocks connected to said top-level test control circuit block, each of said lower-level test control circuit blocks comprising a socket access port (SAP) controller, wherein at least one hierarchical level comprises at least two of the plurality of test control circuit blocks connected together;
wherein test operation is transferred downward and upwards within said hierarchical structure by communicating from each test control circuit block to the test control circuit block at the immediately higher or immediately lower hierarchical level in said hierarchical structure.
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Accused Products
Abstract
A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical. An existing boundary scan may be easily modified for use in the hierarchical structure by adding push instructions to send it to a lower-level test circuit block, and pop instructions to return control to the higher level test circuit block.
51 Citations
20 Claims
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1. A hierarchical test control network for a chip design, comprising:
a plurality of test control circuit blocks in a hierarchical structure having a plurality of hierarchical levels, said test control circuit blocks comprising a top-level test control circuit block having a chip access port (CAP) controller; and
a plurality of lower-level test control circuit blocks, one or more of said lower-level test control circuit blocks at each of said hierarchical levels, at least one of said lower-level test control circuit blocks connected to said top-level test control circuit block, each of said lower-level test control circuit blocks comprising a socket access port (SAP) controller, wherein at least one hierarchical level comprises at least two of the plurality of test control circuit blocks connected together;
wherein test operation is transferred downward and upwards within said hierarchical structure by communicating from each test control circuit block to the test control circuit block at the immediately higher or immediately lower hierarchical level in said hierarchical structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A hierarchical test control network for an integrated circuit, comprising:
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a plurality of test control circuit blocks arranged in a hierarchical structure having a plurality of hierarchical levels, each of said test control circuit blocks comprising a first test data input port, a second test data input port, and a test data output port, at least one of said test control circuit blocks connected to a chip access port;
a common test mode select signal connected to all of said test control circuit blocks;
a common test reset signal connected to all of said test control circuit blocks; and
a common test clock signal connected to all of said test control circuit blocks;
wherein test control circuit blocks at the same hierarchical level each receive at their second test data input port a shared test data output signal from the test data output port of a test control circuit block at the immediately higher hierarchical level, said test control circuit blocks at said same hierarchical level connected together. - View Dependent Claims (14, 15)
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16. A hierarchical test control network for an integrated circuit, comprising:
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a plurality of test control circuit blocks arranged in a hierarchical structure having a plurality of hierarchical levels, each of said test control circuit blocks comprising a first test data input port, a second test data input port, and a test data output port, wherein at least one of said test control circuit blocks is connected to a chip access port, and wherein test control circuit blocks at the same hierarchical level each receive at their second test data input port a common test data output signal from the test data output port of a test control circuit block at the immediately higher hierarchical level, said test control circuit blocks at said same hierarchical level connected together;
a top-level test mode select signal connected to at least one of said test control circuit blocks at the top hierarchical level; and
a test mode select output signal connected from each test control circuit block, except test control circuit blocks at the lowest hierarchical level, to test control circuit blocks at the immediately lower hierarchical level. - View Dependent Claims (17, 18, 19, 20)
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Specification