Method of manufacturing semiconductor device having trench filled up with gate electrode

• US 20030141514A1
• Filed: 01/13/2003
• Published: 07/31/2003
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Hitoshi Yamaguchi, Jun Sakakibara, Takumi Shibata, Toshio Sakakibara, Toshiyuki Morishita
• Original Assignee: Hitoshi Yamaguchi, Jun Sakakibara, Takumi Shibata, Toshio Sakakibara, Toshiyuki Morishita
• Inventors: Morishita, Toshiyuki, Shibata, Takumi, Yamaguchi, Hitoshi, Sakakibara, Jun, Sakakibara, Toshio
• Granted Patent: US 6,696,323 B2
• Time in Patent Office: Days
• US Class Current: 257/107
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 : with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In a semiconductor device, a p-type base region is provided in an n⁻-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n⁺-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n⁺-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n⁺-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the source region, in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region and the source region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein the drain region extends in the semiconductor substrate from the principal surface in the first direction.

3. The semiconductor device according to claim 2, wherein the drain region has an impurity concentration that is uniform in both the first direction and the second direction.

4. The semiconductor device according to claim 2, further comprising:

a support substrate bonded to the back surface of the semiconductor substrate; and

an insulating film interposed between the support substrate and the semiconductor substrate,

wherein the support substrate, the insulating film, and the semiconductor substrate constitute an SOI substrate.

5. The semiconductor device according to claim 4, wherein the trench extends in the first direction and reaches the insulating film.

6. The semiconductor device according to claim 2, wherein the source region, the base region, the drift region and the drain region are arrayed in the second direction in succession.

7. The semiconductor device according to claim 2, wherein the trench extends from the principal surface in the first direction, penetrates the base region, and reaches the drain region.

8. The semiconductor device according to claim 2, wherein the source electrode and the drain electrode are disposed above the principal surface of the semiconductor substrate.

9. The semiconductor device according to claim 2, further comprising a resistance lowering layer provided in one of the drain region and the source region and extending from the principal surface in the first direction, the resistance lowering layer having a resistivity lower than that of the one of the drain region and the source region.

10. The semiconductor device according to claim 1, wherein the drain region has a first drain part extending from the principal surface of the semiconductor substrate in the first direction, and a second drain part integrated with the first drain part and provided at a side of the back surface of the semiconductor substrate.

11. The semiconductor device according to claim 10, wherein:

the source electrode is provided above the principal surface of the semiconductor substrate and electrically connected to the source region and the base region; and

the drain electrode is provided above the back surface of the semiconductor substrate and electrically connected with the drain region.

12. The semiconductor device according to claim 1, wherein the drain region is provided at a side of the back surface of the semiconductor substrate.

13. The semiconductor device according to claim 1, wherein:

the trench includes first and second trenches that are arranged in the semiconductor substrate in a third direction parallel to the principal surface and perpendicular to the second direction; and

the base region is disposed between the first and second trenches and electrically connected with the source electrode.

14. The semiconductor device according to claim 13, wherein:

the base region is provided at both sides of the source region; and

each of the first and second trenches is divided into two parts at a center of the source region.

15. The semiconductor device according to claim 13, wherein:

the base region, the drift region, and the drain region are concentrically disposed about the source region being a center; and

the trench includes a plurality of trenches disposed radially about the source region.

16. The semiconductor device according to claim 13, wherein:

the drift region, the base region and the source region are disposed concentrically about the drain region being a center; and

the trench includes a plurality of trenches disposed radially about the drain region.

17. The semiconductor device according to claim 13, further comprising a gate wiring member connected to the gate electrode, the gate wiring member being connected to the gate electrode an end portion of the trench at a side of the drift region, and provided above a pn junction part provided between the drift region and the base region.

18. The semiconductor device according toclaim 1, wherein:

the drain region extends from the principal surface of the semiconductor substrate in the first direction; and

an impurity diffusion layer of the first conductivity type is provided in the drain region and terminated at the principal surface of the semiconductor substrate.

19. The semiconductor device according to claim 1, wherein:

the source region are provided at only a first side of the trench;

the base region has a first part provided at the first side of the trench and a second part provided at a second side of the trench opposite the first side, the second part being an injection layer and electrically fixed to have a predetermined potential difference with respect to the drain region.

20. The semiconductor device according to claim 19, wherein:

the trench includes a plurality of trenches arranged in a third direction that is parallel to the principal surface and perpendicular to the second direction; and

at least one of the plurality of trenches has the injection layer at the second side thereof.

21. The semiconductor device according to claim 1, further comprising an injection layer of the first conductivity type provided in the drift region at a location remote from the base region and avoiding a region that is to be a channel region.

22. The semiconductor device according to claim 21, wherein the injection layer is provided in contact with a distal end portion of the trench that penetrates the base region from the source region and reaches the drift region.

23. The semiconductor device according to claim 1, further comprising an injection layer of the first conductivity type extending in the semiconductor substrate from the principal surface in the first direction at an opposite side of the drift region with respect to the base region.

24. The semiconductor device according to claim 1, further comprising an injection layer of the first conductivity type provided at a side of the back surface in the semiconductor substrate.

25. The semiconductor device according to claim 1, further comprising an injection layer of the first conductivity type provided in the semiconductor substrate and electrically connected to the gate electrode.

26. The semiconductor device according to claim 25, wherein the injection layer is electrically connected to the gate electrode through a resistor.

27. The semiconductor device according to claim 1, further comprising a contact layer provided in the base region and extending from the principal surface of the semiconductor substrate in the first direction.

28. The semiconductor device according to claim 1, wherein a depth of the trench in the first direction is in a range of 50 μ

m to 300 μ

m.

29. The semiconductor device according to claim 28, wherein the depth of the trench is in a range of 20 μ

m to 100 μ

m.

30. The semiconductor device according to claim 1, wherein the trench extends in the semiconductor substrate in the first direction and is terminated in one of the base region and the source region.

31. The semiconductor device according to claim 1, wherein:

when a voltage is applied to the gate electrode, a channel region is formed in a portion of the base region adjoining the trench, the channel region having a width in the first direction and allowing a current to flow therein in the second direction.

32. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface, extending in the first direction, and penetrating the base region from the source region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region and the source region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.

33. The semiconductor device according to claim 32, wherein:

the drain region extends from the principal surface of the semiconductor substrate in the first direction; and

the drain region has an impurity concentration that is uniform in both the first direction and the second direction.

34. The semiconductor substrate according to claim 33, further comprising:

a support substrate bonded to the back surface of the semiconductor substrate; and

an insulating film interposed between the support substrate and the semiconductor substrate,

wherein the support substrate, the insulating substrate, and the semiconductor substrate constitute an SOI substrate.

35. The semiconductor device according to claim 32, wherein, when a voltage is applied to the gate electrode, a channel region is formed in a portion of the base region adjoining the trench, the channel region having a width in the first direction and allowing a current to flow therein in the second direction.

36. The semiconductor device according to claim 32, wherein the drain region is provided at a side of the back surface of the semiconductor substrate.

37. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a source region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a drift region provided in the semiconductor substrate at an opposite side of the base region with respect to the source region;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the source region in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region and the base region;

a drain electrode electrically connected to the drain region; and

a channel region formed in a portion of the base region adjoining the trench when so that a current flows in the channel region in the first direction when a voltage is applied to the gate electrode, the channel region having a width in the first direction that corresponds to a depth direction of the trench.

38. The semiconductor device according to claim 37, wherein the drain region has a first drain part extending from the principal surface in the first direction and a second drain part integrated with the first drain part and extending in the second direction at a side of the back surface.

39. The semiconductor device according to claim 37, wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.

40. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

an emitter region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a low concentration collector region of the second conductivity type provided in the semiconductor substrate at an opposite side of the base region with respect to the emitter region;

a collector region of the first conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the emitter region, in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

an emitter electrode electrically connected to the emitter region and the base region; and

a collector electrode electrically connected to the collector region,

wherein the low concentration collector region, the base region and the emitter region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.

41. The semiconductor device according to claim 40, wherein:

the collector region extends in the semiconductor substrate from the principal surface in the first direction; and

the collector region has an impurity concentration that is uniform in both the first direction and the second direction.

42. The semiconductor device according to claim 41, further comprising:

a support substrate bonded to the back surface of the semiconductor substrate; and

an insulating film interposed between the support substrate and the semiconductor substrate,

wherein the support substrate, the insulating film, and the semiconductor substrate constitute an SOI substrate.

43. The semiconductor device according to claim 41, wherein the emitter region, the base region, and the collector region are arrayed in the second direction in succession.

44. The semiconductor device according to claim 40, wherein the trench penetrates the base region in the second direction, and reaches the collector region.

45. The semiconductor device according to claim 40, wherein the emitter electrode and the collector electrode are disposed above the principal surface of the semiconductor substrate.

46. The semiconductor device according to claim 40, wherein, when a voltage is applied to the gate electrode, a channel region is formed in a part of the base region adjoining the trench so as to have a width in the first direction corresponding to a depth direction of the semiconductor substrate and so as to allow a current to flow therein in the second direction.

47. The semiconductor device according to claim 46, wherein the collector region has a first collector part extending from the principal surface of the semiconductor substrate in the first direction, and a second collector part integrated with the first collector part and provided at a side of the back surface of the semiconductor substrate.

48. The semiconductor device according to claim 40, wherein the collector region is provided at a side of the back surface of the semiconductor substrate and extends in parallel with the second direction.

49. The semiconductor device according to claim 48, wherein:

the emitter electrode is provided above the principal surface of the semiconductor substrate and electrically connected to the emitter region and the base region; and

the collector electrode is provided above the back surface of the semiconductor substrate and electrically connected with the collector region.

50. The semiconductor device according to claim 40, further comprising a resistance lowering layer provided in one of the collector region and the emitter region, and extending from the principal surface in the first direction, the resistance lowering layer having a resistivity lower than that of the one of the collector region and the emitter region.

51. The semiconductor device according to claim 40, wherein:

the trench includes first and second trenches that are arranged in the semiconductor substrate in a third direction parallel to the principal surface and perpendicular to the second direction; and

the base region is disposed between the first and second trenches and electrically connected with the emitter electrode.

52. The semiconductor device according to. Claim 51, wherein:

the base region is provided at both sides of the emitter region; and

each of the first and second trenches is divided into two parts at a center of the emitter region.

53. The semiconductor device according to claim 40, wherein:

the base region, the low concentration collector region, and the collector region are concentrically disposed about the emitter region being a center; and

the trench includes a plurality of trenches disposed radially about the emitter region.

54. The semiconductor device according to claim 40, wherein:

the low concentration collector region, the base region and the emitter region are disposed concentrically about the collector region being a center; and

the trench includes a plurality of trenches disposed radially about the collector region.

55. The semiconductor device according to claim 40, further comprising a gate wiring member connected to the gate electrode, the gate wiring member being connected to the gate electrode at an end portion of the trench at a side of the low concentration collector region, and provided above a pn junction part provided between the low concentration collector region and the base region.

56. The semiconductor device according to claim 40, wherein:

the collector region extends from the principal surface of the semiconductor substrate in the first direction; and

an impurity diffusion layer of the first conductivity type is provided in the collector region and terminated at the principal surface of the semiconductor substrate.

57. The semiconductor device according to claim 40, wherein:

the emitter region are provided at only a first side of the trench;

the base region has a first part provided at the first side of the trench and a second part provided at a second side of the trench opposite the first side, the second part being an injection layer and electrically fixed to have a predetermined potential difference with respect to the collector region.

58. The semiconductor device according to claim 57, wherein:

the trench includes a plurality of trenches arranged in a third direction that is parallel to the principal surface and perpendicular to the second direction; and

at least one of the plurality of trenches has the injection layer at the second side thereof.

59. The semiconductor device according to claim 40, further comprising an injection layer of the first conductivity type provided in the low concentration collector region at a location remote from the base region and avoiding a region that is to be a channel region.

60. The semiconductor device according to claim 59, wherein the injection layer is provided in contact with a distal end portion of the trench that penetrates the base region from the emitter region and reaches the low concentration collector region.

61. The semiconductor device according t to claim 40, further comprising an injection layer of the first conductivity type extending in the semiconductor substrate from the principal surface in the first direction at an opposite side of the low concentration collector region with respect to the emitter region, wherein;

the collector region is provided at a side of the back surface of the semiconductor substrate.

62. The semiconductor device according to claim 40, further comprising an injection layer of the first conductivity type provided at a side of the back surface of the semiconductor substrate, wherein;

the collector region extends from the principal surface in the first direction.

63. The semiconductor device according to claim 40, wherein the trench is terminated in one of the base region and the emitter region in the first direction.

64. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

an emitter region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a low concentration collector region of the second conductivity type provided in the semiconductor substrate at an opposite side of the base region with respect to the emitter region;

a collector region of the first conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface, extending in the first direction from the principal surface, and penetrating the base region from the emitter region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

an emitter electrode electrically connected to the emitter region and the base region; and

a collector electrode electrically connected to the collector region,

wherein the low concentration collector region, the base region and the emitter region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction.

65. The semiconductor device according to claim 64, wherein:

the collector region extends in the semiconductor substrate from the principal surface in the first direction; and

the collector region has an impurity concentration that is uniform in both the first direction and the second direction.

66. The semiconductor device according to claim 65, further comprising:

a support substrate bonded to the back surface of the semiconductor substrate; and

an insulating film interposed between the support substrate and the semiconductor substrate,

wherein the support substrate, the insulating film, and the semiconductor substrate constitute an SOI substrate.

67. The semiconductor device according to claim 65, wherein the collector region is provided at a side of the back surface of the semiconductor substrate and extends in parallel with the second direction.

68. The semiconductor device according to claim 65, wherein, when a voltage is applied to the gate electrode, a channel region is formed in a part of the base region adjoining the trench so as to have a width in the first direction corresponding to a depth direction of the semiconductor substrate and so as to allow a current to flow therein in the second direction.

69. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

a base region of a first conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

an emitter region of a second conductivity type provided in the base region and extending from the principal surface in the first direction;

a low concentration collector region of the second -conductivity type provided in the semiconductor substrate at an opposite side of the base region with respect to the emitter region;

a collector region of the first conductivity type provided in the semiconductor substrate at a location remote from the base region;

a trench dug from the principal surface and penetrating the base region from the emitter region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

an emitter electrode electrically connected to the emitter region and the base region;

a collector electrode electrically connected to the collector region; and

a channel region formed in a part of the base region adjoining the trench when a voltage is applied to the gate electrode, the channel region having a width in the first direction and allowing a current to flow in therein in the second direction.

70. The semiconductor device according to claim 69, wherein the trench passes through the base region in the second direction that is parallel to the principal surface.

71. The semiconductor device according to claim 70, wherein the collector region is provided at a side of the back surface of the semiconductor substrate.

72. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type, having a principal surface and a back surface at an opposite side of the principal surface;

a source region of a second conductivity type provided in the semiconductor substrate and extending from the principal surface in a first direction perpendicular to the principal surface;

a drain region of the second conductivity type provided in the semiconductor substrate at a location remote from the source region;

a trench dug from the principal surface and extending from the source region to the drain region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode filling the trench through the gate insulating film;

a source electrode electrically connected to the source region; and

a drain electrode electrically connected to the drain region,

wherein the source region, the base region and the drain region respectively have impurity concentrations, each of which is uniform in both the first direction and the second direction; and

wherein, when a voltage is applied to the gate electrode, a channel region is formed in a portion of the semiconductor substrate adjoining the trench so as to a channel width in a depth direction of the trench, and so as to allow a current to flow therein in a direction parallel to the principal surface.

73. A semiconductor device comprising:

a semiconductor substrate having a principal surface and aback surface being an opposite surface of the principal surface;

a first conductivity type base region extending in the semiconductor substrate from the principal surface in a first direction perpendicular to the principal surface;

a second conductivity type source region extending in the base region from the principal surface in the first direction;

a drift region provided at an opposite side of the base region with respect to the source region;

a second conductivity type drain region extending in the semiconductor substrate from the principal surface in the first direction separately from the base region;

a trench dug from the principal surface and penetrating the base region from the source region in a second direction parallel to the principal surface;

a gate insulating film provided on a surface of the trench;

a gate electrode provided on a surface of the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is uniform in a depth direction of the semiconductor substrate.

74. A semiconductor device comprising:

a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

a first conductivity type base region extending in the semiconductor substrate from the principal surface in a first direction perpendicular to the principal surface;

a second conductivity type source region extending in the base region from the principal surface in the first direction;

a drift region provided at an opposite side of the base region with respect to the source region;

a second conductivity type drain region extending in the semiconductor substrate from the principal surface in the first direction separately from the base region;

a trench dug from the principal surface, extending in the semiconductor substrate in the first direction, and penetrating the base region from the source region in a second direction;

a gate insulating film provided on a surface of the trench;

a gate electrode provided on a surface of the gate insulating film;

a source electrode electrically connected to the source region and the base region; and

a drain electrode electrically connected to the drain region,

wherein the drift region, the base region, the source region, and the drain region respectively have impurity concentrations, each of which is uniform in a depth direction of the semiconductor substrate.

75. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a second conductivity type base region by filling up the first trench with a second conductivity type semiconductor;

forming a second trench within the base region and a third trench in the semiconductor substrate at a location remote from the base region, each of the second trench and the third trench extending from the principal surface in the perpendicular direction;

forming a first conductivity type source region by filling up the second trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the third trench with the first conductivity type semiconductor;

forming a fourth trench penetrating the base region from the source region, the fourth trench extending form the principal surface in the perpendicular direction;

forming a gate insulating film in the fourth trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

76. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having-a principal surface and a back surface being an opposite surface of the principal surface;

forming a first trench at a first region of the semiconductor substrate and a second trench at a second region of the semiconductor substrate remote from the first region, each of the first trench and the second trench extending in the semiconductor substrate form the principal surface in a perpendicular direction with respect to the principal surface;

covering the principal surface of the semiconductor substrate with a mask exposing the first trench from an opening of the mask while covering the second trench;

forming a second conductivity type base region in the first trench by diffusing a second conductivity type impurity into the semiconductor substrate from the first trench, through the mask;

removing the mask;

forming a first conductivity type source region by filling up the first trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the second trench with the first conductivity type semiconductor;

forming a third trench in the semiconductor substrate to penetrate the base region from the source region and to extend from the principal surface in the perpendicular direction;

forming a gate insulating film in the third trench;

forming a gate electrode on the gate insulating film to fill up the third trench;

forming a source electrode electrically connected to the source region and the base region; and

forming a drain electrode electrically connected to the drain region.

77. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

forming a first trench at a first region of the semiconductor substrate and a second trench at a second region of the semiconductor substrate remote from the first region, each of the first trench and the second trench extending in the semiconductor substrate form the principal surface in a perpendicular direction with respect to the principal surface;

covering the principal surface of the semiconductor substrate with a mask exposing the second trench from an opening of the mask while covering the first trench;

forming a first conductivity type drift region in the semiconductor substrate by diffusing a first conductivity type impurity into the semiconductor substrate from the second trench, through the mask;

removing the mask;

forming a first conductivity type source region by filling up the first trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the second trench with the first conductivity type semiconductor;

forming a third trench in the semiconductor substrate to penetrate the base region from the source region and to extend from the principal surface in the perpendicular direction;

forming a gate insulating film in the third trench;

forming a gate electrode on the gate insulating film to fill up the third trench;

forming a source electrode electrically connected to the source region and the base region; and

forming a drain electrode electrically connected to the drain region.

78. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift formation film constituting a first conductivity type drift region, in the first trench such that the drift formation film covers an inner wall of the first trench and has a recess;

forming a base formation film constituting a second conductivity type base region in the recess of the drift formation film such that the base formation film covers the drift region in the trench and has a recess;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the drift formation film, the base formation film, and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

82. The method according to any one of claims 78 to 81, wherein the semiconductor substrate is a (110) substrate.

83. The method according to any one of claims 78 to 81, further comprising:

forming a third trench in one of the source region and the drain region, the third trench extending from the principal surface of the semiconductor substrate in the perpendicular direction; and

forming a resistance lowering layer in the third trench.

79. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift formation film constituting a first conductivity type drift region, in the first trench such that the drift formation film covers an inner wall of the first trench and has a recess;

forming a second conductivity type base region at a surface portion of the drift region by doping a second conductivity type impurity into the surface portion of the drift region in the trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the drift formation film and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

80. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift region by doping a second conductivity type impurity into the semiconductor substrate from an inner wall of the first trench;

forming a base region in the drift region by doping the second conductivity type impurity from the inner wall of the first trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

81. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift region by doping a second conductivity type impurity into the semiconductor substrate from an inner wall of the first trench;

forming a base formation film constituting a second conductivity base region, the base formation film covering the drift region in the first trench and having a recess corresponding to the first trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the base formation film and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.