Mass storage array and methods for operation thereof

• US 20030142544A1
• Filed: 08/05/2002
• Published: 07/31/2003
• Est. Priority Date: 01/31/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Maayan, Eduardo, Cohen, Zeev, Dvir, Ran
• Granted Patent: US 6,975,536 B2
• Time in Patent Office: Days
• US Class Current: 365/185.16
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays

Abstract

Apparatus including a virtual ground array, mass storage non-volatile memory device, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. Methods for operating the mass storage device are also disclosed herein.

Claims

1. A method for operating a mass storage device, the method comprising:

operating on a virtual ground array, mass storage non-volatile memory device, which comprises memory cells connected in rows and columns to word lines and bit lines, respectively.

2. The method according to claim 1 wherein said operating comprises at least one of reading, programming and erasing.

3. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits along at least one word line, and said operating comprises performing consecutive accesses to subsets of the bits of said at least one block along said at least one word line.

4. The method according to claim 3 wherein said operating comprises parallel accessing of a subset of the bits of said at least one block, wherein said subset comprises at least one bit of said at least one block.

5. The method according to claim 3 wherein said operating comprises serial accessing of a subset of the bits of said at least one block, wherein said subset comprises at least one bit of said at least one block.

6. The method according to claim 3 and further comprising performing consecutive accesses to said subsets until a portion of the bits of said at least one block are operated upon.

7. The method according to claim 3 and further comprising performing consecutive accesses to said subsets until all the bits of said at least one block are operated upon.

8. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits along at least one word line, and said operating comprises accessing equal-sized subsets of bits.

9. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits along at least one word line, and said operating comprises accessing unequal-sized subsets of bits.

10. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits in virtual ground isolated slices along at least one word line, and said operating comprises accessing subsets of bits that are located at the same location in at least two of said virtual ground isolated slices.

11. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits along at least one word line, and said operating comprises reading said data from one of said subsets and storing said data in a memory location while accessing another one of said subsets.

12. The method according to claim 1 wherein said virtual ground array comprises at least one block of data stored in bits along at least one word line, and said operating comprises driving said at least one word line to an operating voltage level once per a block operation.

13. Apparatus comprising:

a virtual ground array, mass storage non-volatile memory device, comprising memory cells connected in rows and columns to word lines and bit lines, respectively.

14. Apparatus according to claim 13 wherein said virtual ground array device comprises at least one block of data stored in bits along a single word line.

15. Apparatus according to claim 13 wherein said virtual ground array device comprises at least one block of data stored in bits along more than one word line.

16. Apparatus according to claim 13 wherein said virtual ground array device comprises a block of data partitioned into isolated slices.

17. Apparatus according to claim 16 wherein said isolated slices are arranged continuously on a word line.

18. Apparatus according to claim 16 wherein said isolated slices are arranged in separate segments on a word line.

19. Apparatus according to claim 13 and further comprising row decoding circuitry and at least one word line driver adapted to provide access and drive voltages to said word lines.

20. Apparatus according to claim 16 wherein said isolated slices are accessible in parallel.

21. Apparatus according to claim 16 wherein said isolated slices are segmented along said bit lines by select transistors into isolated physical sectors (P-sectors).

22. Apparatus according to claim 21 wherein a bit line in at least one of said P-sectors comprises a local bit line (LBL) connected through a select transistor to a global bit line (GBL).

23. Apparatus according to claim 22 wherein different LBLs corresponding to different P-sectors share a common GBL.

24. Apparatus according to claim 22 wherein different LBLs within a P-sector share a common GBL.

25. Apparatus according to claim 16 wherein at least one bit in at least one of said isolated slices is accessible through a global bit line.

26. Apparatus according to claim 13 wherein at least one of said memory cells comprises a non-conducting charge trapping layer.

27. Apparatus according to claim 26 wherein at least one of said memory cells is a nitride, read only memory (NROM) cell.