Intermediate wake mode to track sleep clock frequency in a wireless communication device

• US 20030144020A1
• Filed: 07/26/2002
• Published: 07/31/2003
• Est. Priority Date: 01/31/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Achour, Baaziz, Challa, Raghu, Hughes, Robbin D.
• Granted Patent: US 6,980,823 B2
• Time in Patent Office: Days
• US Class Current: 455/522
• CPC Class Codes: H04B 1/70756 Jumping within the code, i.e. masking or slewing H04B1/70758 takes precedence
• CPC Class Codes: H04B 2201/70709 with discontinuous detection
• CPC Class Codes: H04W 52/0216 using a pre-established activity schedule, e.g. traffic indication frame
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Various techniques for improving a wireless communication device are described. The techniques may include reducing power in a wireless communication device for a first sleep period and then increasing power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of the sleep clock. The method may further include reducing power in the wireless communication device for a second sleep period after the intermediate wake period. The intermediate wake mode implemented during the intermediate period can be used to estimate the error of the sleep clock without performing one or more tasks associated with an awake mode, such as demodulation. The techniques may facilitate the effective use of low frequency low power clocks for sleep mode, even when relatively large slot cycles are defined within a slotted paging system.

Claims

1. A method comprising:

reducing power in a wireless communication device for a first sleep period;

increasing power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of a sleep clock without performing a demodulation; and

reducing power in the wireless communication device for a second sleep period after the intermediate wake period.

2. The method of claim 1, further comprising increasing power in the wireless communication device for an awake period after the second sleep period.

3. The method of claim 1, wherein the intermediate wake period is a first intermediate wake period, the method further comprising increasing power in the wireless communication device for a second intermediate wake period after the second sleep period to estimate another error of the sleep clock without performing a demodulation.

4. The method of claim 1, further comprising during the intermediate wake period:

estimating the error of the sleep clock based on a time that a pilot signal is received;

correcting for the error in the sleep clock; and

not demodulating a paging signal.

5. The method of claim 2, further comprising during the awake period:

estimating the error of the sleep clock based on a time that a pilot signal is received;

correcting for the error in the sleep clock; and

demodulating a paging signal.

6. The method of claim 1, further comprising dynamically defining a length of a slot cycle and adjusting a number of intermediate wake periods to occur in a slot cycle based on the length of the slot cycle.

7. A computer-readable medium comprising program code that when executed:

reduces power in a wireless communication device for a first sleep period;

increases power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of a sleep clock without performing a demodulation; and

reduces power in the wireless communication device for a second sleep period after the intermediate wake period.

8. The computer-readable medium of claim 7, wherein the program code when executed increases power in the wireless communication device for an awake period after the second sleep period.

9. The computer-readable medium of claim 7, wherein the intermediate wake period is a first intermediate wake period, wherein the program code when executed increases power in the wireless communication device for a second intermediate wake period after the second sleep period to estimate another error of the sleep clock without performing a demodulation.

10. The computer-readable medium of claim 7, wherein the program code when executed during the intermediate wake period:

estimates the error of the sleep clock based on a time that a pilot signal is received;

corrects for the error in the sleep clock; and

does not cause a paging signal to be demodulated.

11. The computer-readable medium of claim 8, wherein the program code when executed during the awake period:

estimates the error of the sleep clock based on a time that a paging signal is received;

corrects for the error in the sleep clock; and

causes a paging signal to be demodulated.

12. The computer-readable medium of claim 7, wherein the program code when executed dynamically defines a length of a slot cycle and adjusts a number of intermediate wake periods to occur in a slot cycle based on the length of the slot cycle.

13. A controller for use in a wireless communication device having a sleep clock, the controller comprising:

means for reducing power in the wireless communication device for a first sleep period;

means for increasing power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of the sleep clock without causing a signal to be demodulated; and

means for reducing power in the wireless communication device for a second sleep period after the intermediate wake period.

14. The controller of claim 13, wherein the controller increases power in the wireless communication device for an awake period after the second sleep period.

15. The controller of claim 13, wherein the intermediate wake period is a first intermediate wake period, wherein the controller increases power in the wireless communication device for a second intermediate wake period after the second sleep period to estimate another error of the sleep clock without performing a demodulation.

16. The controller of claim 13, wherein during the intermediate wake period the wireless communication device receives a pilot signal;

and

the controller estimates the error in the sleep clock, corrects for the error in the sleep clock, and does not cause a paging signal to be demodulated.

17. The controller of claim 14, wherein during the awake period the wireless communication device receives a pilot signal and a paging signal;

and

the controller estimates the error in the sleep clock, corrects for the error in the sleep clock, and causes the paging signal to be demodulated.

18. The controller of claim 17, wherein the controller causes the paging signal to be demodulated by assigning RAKE receiver fingers to demodulate the paging signal.

19. The controller of claim 13, wherein the controller dynamically defines a length of a slot cycle, and adjusts a number of intermediate wake periods to occur in a slot cycle based on the length of the slot cycle.

20. An apparatus comprising:

a memory that stores executable instructions; and

a processor coupled to the memory that executes the instructions to reduce power in a wireless communication device for a first sleep period, increase power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of a sleep clock without demodulating a signal, and reduce power in the wireless communication device for a second sleep period after the intermediate wake period.

21. The apparatus of claim 20, wherein the processor executes the instructions to dynamically define a length of a slot cycle and adjust a number of intermediate wake periods to occur in a slot cycle based on the length of the slot cycle.

22. The apparatus of claim 20, wherein the processor executes the instructions to increase power in the wireless communication device for an awake period after the second sleep period.

23. The apparatus of claim 20, wherein the intermediate wake period is a first intermediate wake period, wherein the processor executes the instructions to increase power in the wireless communication device for a second intermediate wake period after the second sleep period to estimate another error in the sleep clock without performing a demodulation.

24. An apparatus comprising:

means for reducing power in a wireless communication device for a first sleep period;

means for increasing power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of a sleep clock without performing a demodulation; and

means for reducing power in the wireless communication device for a second sleep period after the intermediate wake period.

25. The apparatus of claim 24, further comprising means for increasing power in the wireless communication device for an awake period after the second sleep period.

26. The apparatus of claim 24, wherein the intermediate wake period is a first intermediate wake period, the apparatus further comprising means for increasing power in the wireless communication device for a second intermediate wake period after the second sleep period to estimate another error in the sleep clock without performing a demodulation.

27. The apparatus of claim 24, further comprising:

means for receiving a pilot signal during the intermediate wake period;

means for estimating the error in the sleep clock during the intermediate wake period;

means for correcting for the error in the sleep clock; and

means for not demodulating a paging signal during the intermediate wake period.

28. The apparatus of claim 25, further comprising:

means for receiving a pilot signal during the awake period;

means for estimating the error in the sleep clock during the awake period;

means for correcting for the error in the sleep clock; and

means for demodulating a paging signal during the awake period.

29. The apparatus of claim 24, further comprising means for dynamically defining a length of a slot cycle and adjusting a number of intermediate wake periods to occur in a slot cycle based on the length of the slot cycle.