Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface

• US 20030146518A1
• Filed: 02/27/2003
• Published: 08/07/2003
• Est. Priority Date: 02/24/1999
• Status: Active Grant

• Current Assignee: Junichi Hikita, Koji Yamamoto, Yoshikazu Nakagawa
• Original Assignee: Junichi Hikita, Koji Yamamoto, Yoshikazu Nakagawa
• Inventors: Yamamoto, Koji, Hikita, Junichi, Nakagawa, Yoshikazu
• Granted Patent: US 6,965,166 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/141 : Disposition
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/17517 : including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/81136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81139 : Guiding structures on the body
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

Claims

1. A semiconductor device, comprising:

a first semiconductor chip;

a second semiconductor chip bonded to the first semiconductor chip in a stacked relation; and

a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other with use of a depression-projection engagement.

2. A semiconductor device as set forth in claim 1, wherein the registration structure includes:

a registration recess provided on a surface of the first semiconductor chip opposed to the second semiconductor chip; and

a registration projection provided on a surface of the second semiconductor chip opposed to the first semiconductor chip for engagement with the registration recess.

3. A semiconductor device as set forth in claim 2, wherein the registration projection is a spherical member provided on the surface of the second semiconductor chip.

4. A semiconductor device as set forth in claim 3,

wherein the second semiconductor chip has a bump for electrical connection to the first semiconductor chip,

wherein the spherical member has a radius such that a distance between a center thereof and the surface of the second semiconductor chip is greater than a height of the bump as measured from the surface of the second semiconductor chip.

5. A semiconductor device as set forth in claim 2, wherein the recess is a pad provided on the first semiconductor chip.

6. A semiconductor device as set forth in claim 2, wherein the recess is a recess formed in a semiconductor substrate which serves as a base of the first semiconductor chip.

7. A semiconductor device as set forth in claim 2, wherein the recess is a recess formed in an insulating film provided on a semiconductor substrate which serves as a base of the first semiconductor chip.

8. A semiconductor device as set forth in claim 2,

wherein the registration recess is formed in a first bump provided on the surface of the first semiconductor chip,

wherein the registration projection is a second bump provided on the surface of the second semiconductor chip.

9. A semiconductor device as set forth in claim 8, wherein the first bump and the second bump respectively have mating surfaces to be bonded to each other, and the mating surfaces of the first and second semiconductor chips have different areas.

10. A semiconductor device as set forth in claim 9, wherein the mating surface of the first bump has a greater area than the mating surface of the second bump.

11. A semiconductor device as set forth in claim 9, wherein the mating surface of the first bump has a smaller area than the mating surface of the second bump.

12. A semiconductor device as set forth in claim 1, wherein the registration structure includes:

a first registration recess provided on a surface of the first semiconductor chip opposed to the second semiconductor chip;

a second registration recess provided on a surface of the second semiconductor chip opposed to the first semiconductor chip; and

a spherical member held between the first and second registration recesses.

13. A semiconductor device as set forth in claim 12, wherein both or either of the first registration recess and the second registration recess is a groove.

14. A semiconductor device as set forth in claim 13, wherein the groove is a groove formed in a peripheral region surrounding a device formation region.

15. A semiconductor device as set forth in claim 14, wherein the groove is a continuous groove entirely surrounding the device formation region.

16. A semiconductor device as set forth in claim 14, wherein the groove includes a plurality of discontinuous grooves.

17. A semiconductor device as set forth in claim 14, wherein the peripheral region is a scribe line region.

18. A semiconductor device as set forth in claim 14, wherein the first or second semiconductor chip has a peripheral bump surrounding the device formation region thereof, and the groove is a groove formed in the peripheral bump.

19. A semiconductor device as set forth in claim 12,

wherein the first or second semiconductor chip has a bump for electrical connection therebetween,

wherein the spherical member has a radius such that a center thereof is located at a higher level than a top surface of the bump when the spherical member is placed in the first or second registration recess before assembling.

20. A semiconductor chip which is to be bonded to a surface of a solid body, the semiconductor chip comprising a projection or a recess provided on a surface thereof for positioning thereof with respect to the surface of the solid body.

21. A semiconductor chip as set forth in claim 20, wherein the projection is a spherical member.

22. A semiconductor chip as set forth in claim 21, further comprising a bump for electrical connection to the solid body,

wherein the spherical member has a radius such that a distance between a center thereof and the surface of the semiconductor chip is greater than a height of the bump as measured from the surface of the semiconductor chip.

23. A semiconductor chip as set forth in claim 20, wherein the recess or the projection is provided on a mating surface of a bump for electrical connection to the solid body.

24. A semiconductor chip as set forth in claim 20, wherein the recess is a groove.

25. A semiconductor chip as set forth in claim 24, wherein the groove is a groove formed in a peripheral region surrounding a device formation region of the semiconductor chip.

26. A semiconductor chip as set forth in claim 25, wherein the peripheral region is a scribed line region.

27. A semiconductor chip as set forth in claim 25, further comprising a peripheral bump provided as surrounding the device formation region,

wherein the groove is a groove formed in the peripheral bump.

28. A semiconductor device, comprising:

a first semiconductor chip;

a second semiconductor chip bonded to the first semiconductor chip in a stacked relation;

a first bump formed on a surface of the first semiconductor chip; and

a second bump formed on a surface of the second semiconductor chip;

wherein the first and second bumps respectively have mating surfaces to be bonded to each other, and the mating surfaces of the first and second bumps having different areas.

29. A semiconductor device as set forth in claim 28,

wherein the mating surface of the first bump is of a concave shape and has a greater area than the mating surface of the second bump,

wherein the mating surface of the second bump is of a convex shape.

30. A semiconductor device as set forth in claim 28,

wherein the mating surface of the first bump is of a convex shape and has a greater area than the mating surface of the second bump,

wherein the mating surface of the second bump is of a concave shape.

31. A semiconductor device assembling process, comprising the steps of:

forming a registration recess on a surface of a first semiconductor chip;

forming a registration recess on a surface of a second semiconductor chip;

placing a spherical member on the registration recess of the first semiconductor chip;

stacking the first and second semiconductor chips with the spherical member being held between the registration recesses of the first and second semiconductor chips; and

bonding the stacked first and second semiconductor chips to each other.

32. A process as set forth in claim 31, wherein the bonding step includes the step of pressing the first and second semiconductor chips against each other to crush the spherical member.