Thin film transistor substrate and method of manufacturing the same

• US 20030153110A1
• Filed: 12/09/2002
• Published: 08/14/2003
• Est. Priority Date: 12/18/2001
• Status: Active Grant

• Current Assignee: Unified Innovative Technology, LLC
• Original Assignee: Fujitsu Display Technologies Corporation (Fujitsu Limited)
• Inventors: Yaegashi, Hiroyuki, Watanabe, Takuya, Kurosawa, Yoshio, Hotta, Kazushige, Sato, Seii
• Granted Patent: US 6,887,744 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an interlayer insulating film which is a film stack with mutually different dielectric constants and which covers the gate electrode, a source region contact hole and a drain region contact hole which are formed on the interlayer insulating film, a pixel electrode connected to the source region through the source region contact hole, a first conductive film connected to the drain region through the drain region contact hole and formed of the same film as that of the pixel electrode, and a second conductive film connected to the drain region through the first conductive film.

Claims

1. A thin film transistor substrate comprising:

an insulating substrate;

a semiconductor layer formed on or above the insulating substrate, the semiconductor layer including a source region and a drain region;

a gate insulating film formed on the semiconductor layer;

a gate electrode formed on the gate insulating film;

an interlayer insulating film made of a film stack of a plurality of insulating films having mutually different dielectric constants, the interlayer insulating film covering the gate electrode and the semiconductor layer;

a source region contact hole formed in the interlayer insulating film on a source region of the semiconductor layer;

a drain region contact hole formed in the interlayer insulating film on a drain region of the semiconductor layer;

a pixel electrode connected to the source region through the source region contact hole;

a first conductive film connected to the drain region through the drain region contact hole, the first conductive film being formed of the same film as a film of the pixel electrode; and

a second conductive film connected to the drain region through the first conductive film.

2. The thin film transistor substrate according to claim 1, further comprising:

a gate busline formed of the same film as a film of the gate electrode;

a gate busline region contact hole formed in the inter layer insulating film on the gate busline;

a third conductive film connected to the gate busline through the gate busline region contact hole, the third conductive film being formed of the same film as the film of the pixel electrode; and

a fourth conductive film connected to the gate busline through the third conductive film, the fourth conductive film being formed of the same film as the second conductive film.

3. The thin film transistor substrate according to claim 1,

wherein the pixel electrode is any one of an ITO film and a SnO₂ film, and

the gate electrode is a film stack having any one of an aluminum (Al) film and a film containing aluminum (Al), and a refractory metal film, which are stacked from bottom to top.

4. The thin film transistor substrate according to claim 1,

wherein the interlayer insulating film is a film stack including a silicon oxide film and a silicon nitride film, which are stacked from bottom to top.

5. The thin film transistor substrate according to claim 3,

wherein the refractory metal film is anyone of a metal film and an alloyed film selected from the group consisting of titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta) and tungsten (W).

6. The thin film transistor substrate according to claim 1,

wherein the interlayer insulating film is a film stack including an inorganic insulating film and a photosensitive resin insulating film, which are stacked from bottom to top.

7. The thin film transistor substrate according to claim 6,

wherein the inorganic insulating film is any one of a silicon nitride film and a film stack including a silicon nitride film.

8. The thin film transistor substrate according to claim 1,

wherein the gate insulating film has protruding portions protruding from both edges of the gate electrode by 0.3 to 2 μ

m, respectively,

the semiconductor layer includes low concentration impurity regions with a lower concentration than an impurity concentration of the source region or the drain region between a channel region under the gate electrode and the source region or the drain region, and the low concentration impurity regions are respectively formed under the protruding portions of the gate insulating film symmetrically with respect to the gate electrode.

9. A thin film transistor substrate comprising:

semiconductor layers formed on or above an insulating substrate;

gate insulating films formed on the semiconductor layers; and

a one conductivity type channel transistor and a opposite conductivity type channel transistor respectively including gate electrodes formed on the gate insulating films,

wherein the semiconductor layer for the one conductivity type channel transistor includes a channel region under the gate electrode, an LDD region, a source region and a drain region, and the gate insulating film for the one conductivity type channel transistor is patterned and formed on the channel region and the LDD region, and

the semiconductor layer for the opposite conductivity type channel transistor includes a channel region under the gate electrode, a source region and a drain region, and the gate insulating film for the opposite conductivity type channel transistor is formed so as to cover the semiconductor layer for the opposite conductivity type channel transistor except for a predetermined portions on the source and drain regions of the opposite conductivity type channel transistor.

10. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming a pattern of a semiconductor layer on or above an insulating substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film;

introducing impurities into portions of the semiconductor layer, which are to be a source region and a drain region;

forming an interlayer insulating film including a plurality of insulating films with mutually different dielectric constants on the semiconductor layer and the gate electrode;

forming contact holes in portions of the interlayer insulating film, the portions being at least on the source region and the drain region;

forming a transparent conductive film on the interlayer insulating film and inner surfaces of the contact holes;

forming a metal film on the transparent conductive film;

forming a interconnection electrode in a portion including the contact hole of the drain region by patterning the metal film while using the transparent conductive film as an etch stop layer; and

forming a pixel electrode connected to the source region through the contact hole and forming the interconnection electrode connected to the drain region through the transparent conductive film in the contact hole by patterning the transparent conductive film.

11. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming a pattern of a semiconductor layer on or above an insulating substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film;

introducing impurities into portions of the semiconductor layer, which are to be a source region and a drain region;

forming an interlayer insulating film including a plurality of insulating films with mutually different dielectric constants on the semiconductor layer and the gate electrode;

forming contact holes in portions of the interlayer insulating film, the portions being at least on the source region and the drain region;

forming a transparent conductive film on the interlayer insulating film and inner surfaces of the contact holes;

forming a metal film on the transparent conductive film;

forming a pattern of a resist film on the metal film so that a thickness of a portion for a formation of a pixel electrode connected with the source region is thinner than a thickness of a portion for a formation of a interconnection electrode connected with the drain region;

forming the interconnection electrode by etching the metal film and the transparent conductive film while using the resist film as a mask;

selectively removing the portion of the resist film for the formation of the pixel electrode and leaving the portion of the resist film for the formation of the interconnection electrode; and

forming the pixel electrode by etching a portion of the metal film where the pixel electrode is formed while using the portion of the resist film for the formation of the interconnection electrode as a mask and using the transparent conductive film as an etch stop layer.

12. A method of manufacturing a thin film transistor substrate, comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming a structure in which a gate insulating film for the opposite conductivity type channel transistor and the gate electrode for the opposite conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the opposite conductivity type channel transistor, are stacked from bottom to top on the semiconductor layer for the opposite conductivity type channel transistor, and forming a pattern of a covering film stack in which a gate insulating film and a conductive film are stacked, the covering film stack covering the semiconductor layer for the one conductivity type channel transistor, by patterning the conductive film and the gate insulating film,;

forming predetermined source and drain regions for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor while using at least anyone of the gate electrode for the opposite conductivity type channel transistor and the gate insulating film therefor as a mask;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor, are stacked from bottom to top, by patterning the covering film stack; and

forming predetermined source and drain regions for the one conductivity type channel transistor by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefor as a mask.

13. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming the gate electrode for the opposite conductivity type channel transistor on the semiconductor layer for the opposite conductivity type channel transistor, and forming a pattern of a covering conductive film which covers the semiconductor layer for the one conductivity type channel transistor by patterning the conductive film;

forming a source region and a drain region for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor through the gate insulating film while using the gate electrode for the opposite conductivity type channel transistor as a mask,;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor, are stacked from bottom to top, by patterning the covering conductive film and the gate insulating film; and

forming predetermined source and drain regions for the one conductivity type channel transistor, by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefor as a mask.

14. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor are stacked from bottom to top on the semiconductor layer for the one conductivity type channel transistor, and forming a pattern of a covering film stack in which a gate insulating film and a conductive film are stacked, the covering film stack covering the semiconductor layer for the opposite conductivity type channel transistor, by patterning the conductive film and the gate insulating film;

forming a source region and a drain region for the one conductivity type channel transistor by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefor as a mask;

patterning a resist film delimiting a region for forming the gate electrode for the opposite conductivity type channel transistor on the covering film stack and covering the semiconductor layer for the one conductivity type channel transistor and the gate electrode therefor;

forming the gate electrode for the opposite conductivity type channel transistor, the gate electrode having a predetermined width equal to or wider than a width of the resist film by etching the covering film stack while using the resist film as a mask; and

forming source and drain regions for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor while using at least anyone of the resist film and the gate electrode for the opposite conductivity type channel transistor as a mask.