Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 20030154357A1
• Filed: 03/07/2003
• Published: 08/14/2003
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation), Much Shelist Freed Ament & Rubenstein, PC
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Scheuermann, Walter James, Master, Paul L., Hogenauer, Eugene
• Granted Patent: US 7,325,123 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Claims

1. An integrated circuit comprising:

a plurality of computational elements, a first computational element of the plurality of computational elements having a first fixed architecture and a second computational element of the plurality of computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;

a plurality of switching elements coupled to the plurality of computational elements, the plurality of switching elements capable of configuring the plurality of computational elements for performance of a first function of a plurality of functions in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of a second function of the plurality of functions in response to second configuration information, the first function being different than the second function.

2. The integrated circuit of claim 1 wherein the plurality of switching elements is capable of configuring the plurality of computational elements for performance of the first function by providing a first plurality of connections between a plurality of inputs and a plurality of outputs of the plurality of computational elements, and is capable of reconfiguring the plurality of computational elements for performance of the second function by providing a second plurality of connections between the plurality of inputs and the plurality of outputs of the plurality of computational elements.

3. The integrated circuit of claim 1 wherein the first computational element is capable of performing a first data operation of a plurality of data operations, and wherein the second computational element is capable of performing a second data operation of the plurality of data operations, the first data operation being different than the second data operation.

4. The integrated circuit of claim 3, wherein the plurality of data operations comprises at least two of the following data operations:

move, input, output, add, subtract, multiply, complex multiply, divide, shift, and multiply and accumulate (MAC).

5. The integrated circuit of claim 1, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures comprising at least two specific architectures for performance of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, synchronization, queuing, over sampling, under sampling, adaptation, configuration, reconfiguration, control, input, output, and field programmability.

6. The integrated circuit of claim 1, further comprising:

a first network coupled to the plurality of computational elements, the first network capable of transferring real time data to the plurality of computational elements.

7. The integrated circuit of claim 6, wherein the first network is capable of routing the real time data through a plurality of switching elements for point-to-point data streaming.

8. The integrated circuit of claim 6, further comprising:

a second network coupled to the plurality of computational elements, the second network capable of routing message and control information between and among the plurality of computational elements.

9. The integrated circuit of claim 8, wherein the second network is capable of routing message and control information through a routing procedure selected from a plurality of routing procedures, the plurality of routing procedures comprising at least one of the following routing procedures:

a round-robin routing procedure, a token ring routing procedure, cross-point switching, four-way switching, or arbitration.

10. The integrated circuit of claim 1, wherein the plurality of computational elements are grouped together as an adaptive execution unit for performance of a plurality of algorithms.

11. The integrated circuit of claim 10, wherein the plurality of algorithms comprises at least two of the following algorithms:

a radix-2 Fast Fourier Transformation (FFT), a radix-4 Fast Fourier Transformation (FFT), a radix-2 inverse Fast Fourier Transformation (IFFT), a radix-4 inverse Fast Fourier Transformation (IFFT)a one-dimensional Discrete Cosine Transformation (DCT), a multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, convolutional encoding, scrambling, puncturing, interleaving, modulation mapping, Golay correlation, OVSF code generation, Haddamard Transformation, Turbo Decoding, bit correlation, Griffiths LMS algorithm, variable length encoding, uplink scrambling code generation, downlink scrambling code generation, downlink despreading, uplink spreading, uplink concatenation, Viterbi encoding, Viterbi decoding, cyclic redundancy coding (CRC), complex multiplication, data compression, motion compensation, channel searching, channel acquisition, and multipath correlation.

12. The integrated circuit of claim 10, further comprising:

a node wrapper having a non-adaptive fixed architecture, the node wrapper coupled to the adaptive execution unit and capable of directing the configuring and reconfiguring of the plurality of computational elements of the adaptive execution unit.

13. The integrated circuit of claim 12, wherein the node wrapper is further capable of performing data decoding, data distribution, input data buffering, output data buffering, data aggregation, and data selection.

14. The integrated circuit of claim 12, wherein a first adaptive execution unit of a plurality of adaptive execution units comprises a first selection of computation elements from the plurality of computational elements to form a first reconfigurable arithmetic node for performance of Fast Fourier Transformation (FFT) and Discrete Cosine Transformation (DCT).

15. The integrated circuit of claim 14, wherein a second adaptive execution unit of the plurality of adaptive execution units comprises a second selection of computation elements from the plurality of computational elements to form a second reconfigurable arithmetic node, the second selection being different than the first selection, for performance of at least two of the following algorithmic elements:

multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, OVSF code generation, Haddamard Transformation, bit-wise WCDMA Turbo interleaving, WCDMA uplink concatenation, WCDMA uplink repeating, and WCDMA uplink real spreading and gain scaling.

16. The integrated circuit of claim 14, wherein a third adaptive execution unit of the plurality of adaptive execution units comprises a third selection of computation elements from the plurality of computational elements to form a bit manipulation node, the third selection being different than the first selection, for performance of at least two of the following algorithmic elements:

variable and multiple rate convolutional encoding, scrambling code generation, puncturing, interleaving, modulation mapping, complex multiplication, Viterbi algorithm, Turbo encoding, Turbo decoding, correlation, linear feedback shifting, downlink despreading, uplink spreading, CRC encoding, de-puncturing, and de-repeating.

17. The integrated circuit of claim 14, wherein a fourth adaptive execution unit of the plurality of adaptive execution units comprises a fourth selection of computation elements from the plurality of computational elements to form a reconfigurable filter node, the fourth selection being different than the first selection, for performance of at least two of the following algorithmic elements:

adaptive finite impulse response (FIR) filtering, Griffith'"'"'s LMS algorithm, and RRC filtering.

18. The integrated circuit of claim 14, wherein a fifth adaptive execution unit of the plurality of adaptive execution units comprises a fifth selection of computation elements from the plurality of computational elements to form a reconfigurable finite state machine node, the fifth selection being different than the first selection, for performance of at least two of the following processes:

control processing;

routing data and control information between and among the plurality of computational elements;

directing and scheduling the configuration of the plurality of computational elements for performance of the first function and the reconfiguration of the plurality of computational elements for performance of the second function;

timing and scheduling the configuration and reconfiguration of the plurality of heterogeneous computational elements with corresponding data;

controlling power distribution to the plurality of heterogeneous computational elements and the interconnection network; and

selecting the first configuration information and the second configuration information from a singular bit stream comprising data commingled with a plurality of configuration information.

19. The integrated circuit of claim 14, wherein a sixth adaptive execution unit of the plurality of adaptive execution units comprises a sixth selection of computation elements from the plurality of computational elements to form a reconfigurable multimedia node, the sixth selection being different than the first selection, for performance of at least two of the following algorithmic elements:

radix-4 Fast Fourier Transformation (FFT);

multi-dimensional radix-2 Discrete Cosine Transformation (DCT);

Golay correlation;

adaptive finite impulse response (FIR) filtering;

Griffith'"'"'s LMS algorithm; and

RRC filtering.

20. The integrated circuit of claim 14, wherein a seventh adaptive execution unit of the plurality of adaptive execution units comprises a seventh selection of computation elements from the plurality of computational elements to form a reconfigurable hybrid node, the seventh selection being different than the first selection, for performance of arithmetic functions and bit manipulation functions.

21. The integrated circuit of claim 14, wherein an eighth adaptive execution unit of the plurality of adaptive execution units comprises an eighth selection of computation elements from the plurality of computational elements to form a reconfigurable input and output (I/O) node, the eighth selection being different than the first selection, for adaptation of input and output functionality for a plurality of types of I/O standards, the plurality of types of I/O standards comprising standards for at least two of the following:

PCI busses, Universal Serial Bus types one and two (USB1 and USB2), and small computer systems interface (SCSI).

22. The integrated circuit of claim 14, wherein a ninth adaptive execution unit of the plurality of adaptive execution units comprises a ninth selection of computation elements from the plurality of computational elements to form a reconfigurable operating system node, the ninth selection being different than the first selection, for storing and executing a selected operating system of a plurality of operating systems.

23. An adaptive system comprising:

a plurality of adaptive nodes, a first node of the plurality of nodes having a first adaptive execution unit and a second node of the plurality of nodes having a second adaptive execution unit, a first architecture of the first adaptive execution unit being different than a second architecture of the second adaptive execution unit, wherein the first adaptive execution unit is capable of being adapted for a first plurality of algorithms and the second adaptive execution unit is capable of being adapted for a second plurality of algorithms; and

an interconnection network coupled to the plurality of nodes, the interconnection network having a plurality of routing elements to selectively route a data packet to a selected node of the plurality of nodes.

24. The adaptive system of claim 23 wherein the plurality of adaptive nodes are further coupled to each other in a by-four fractal arrangement through the interconnection network.

25. The adaptive system of claim 24 wherein each by-four fractal arrangement has a routing element to route the data packet to a selected adaptive node of the plurality of adaptive nodes.

26. The adaptive system of claim 24 wherein a plurality of by-four fractal arrangements of the plurality of adaptive nodes has a routing element to route the data packet to a selected by-four fractal arrangement of the plurality of by-four fractal arrangements.

27. The adaptive system of claim 23 wherein the data packet has a data structure comprising:

a first data field for routing information;

a second data field for security information;

a third data field for a service code;

a fourth data field for an auxiliary code;

and a fifth data field for a data word.

28. The adaptive system of claim 27 wherein the service code is selected from a plurality of service codes, the plurality of service codes comprising at least two of the following designations:

an acknowledgement message;

a memory read;

a memory write;

a memory move; and

a memory address.

29. The adaptive system of claim 27 wherein the auxiliary code comprises a selected task designation of a plurality of task designations.

30. The adaptive system of claim 23 wherein the first adaptive execution unit and the second adaptive execution unit are each further comprised of:

a plurality of computational elements, a first computational element of the plurality of computational elements having a first fixed architecture and a second computational element of the plurality of computational elements having a second fixed architecture, the first fixed architecture being different from the second fixed architecture;

a plurality of switching elements coupled to the plurality of computational elements, the plurality of switching elements capable of configuring the plurality of computational elements for performance of a first function of a plurality of functions in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of a second function of the plurality of functions in response to second configuration information, the first function being different than the second function.

31. The adaptive system of claim 23 wherein the plurality of adaptive nodes are further coupled to each other in a tree topology.

32. The adaptive system of claim 23, further comprising:

a kernel (K) node coupled to the plurality of adaptive nodes through the interconnection network, the kernel node capable of providing an operating system for the adaptive system.

33. The adaptive system of claim 32, further comprising:

a memory coupled to the interconnection network; and

a host system input and output coupled to the interconnection network.

34. The adaptive system of claim 23, wherein for each adaptive node of the plurality of adaptive nodes, the interconnection network further comprises:

a first routing element coupled to a common node input and coupled to a plurality of peer node inputs; and

a first multiplexer coupled to the first routing element for input through the first routing element, the multiplexer further coupled to a real time data input and a feedback input.

35. The adaptive system of claim 34, wherein for each adaptive node of the plurality of adaptive nodes, the interconnection network further comprises:

a real time data output;

a second routing element having an input coupled to the adaptive node output and providing a plurality of outputs for the plurality of peer node inputs and for a common output.

36. An integrated circuit comprising:

an input pipeline register to receive an input data packet;

a memory capable of storing the input data packet;

a hardware task manager capable of processing a plurality of tasks and determining that a first task from the plurality of tasks is capable of being performed and that a second task from the plurality of tasks is capable of being performed, the first task being different than the second task;

a data distributor coupled to the input pipeline register, to the memory, and to the hardware task manager, the data distributor capable of distributing the input data packet to the hardware task manager and further capable of distributing the input data packet to the memory;

an adaptive execution unit coupled to the hardware task manager and to the memory, the adaptive execution unit capable of configuring to perform the first task and capable of performing the first task using the input data packet, the adaptive execution unit further capable of reconfiguring to perform the second task and capable of performing the second task, the adaptive execution unit further capable of generating an output data packet from the performance of the first task and the second task;

a data selector coupled to the hardware task manager, to the adaptive execution unit and to the memory, the data selector capable of determining routing for the output data packet; and

an output pipeline register coupled to the data selector to receive the output data packet.

37. The integrated circuit of claim 36, wherein the adaptive execution unit comprises:

a plurality of computational elements, a first computational element of the plurality of computational elements having a first fixed architecture and a second computational element of the plurality of computational elements having a second fixed architecture, the first fixed architecture being different from the second fixed architecture;

a plurality of switching elements coupled to the plurality of computational elements, the plurality of switching elements capable of configuring the plurality of computational elements for performance of a first function of a plurality of functions in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of a second function of the plurality of functions in response to second configuration information, the first function being different than the second function.

38. The integrated circuit of claim 37, wherein the plurality of switching elements are comprised of a plurality of multiplexers.

39. The integrated circuit of claim 38, wherein the plurality of switching elements is further comprised of a plurality of demultiplexers.

40. The integrated circuit of claim 39, wherein the plurality of switching elements is further comprised of a plurality of routing elements.

41. The integrated circuit of claim 36, further comprising:

an address register coupled to the hardware task manager and to the adaptive execution unit; and

a direct memory access engine coupled to the hardware task manager and to the adaptive execution unit.

42. The integrated circuit of claim 36, wherein the input pipeline register is capable of receiving the input data packet containing a plurality of fields, the plurality of fields comprising a first data field for routing information;

a second data field for security information;

a third data field for a service code, the service code designating an acknowledgement message, a memory read, a memory write, a memory move, or a memory address;

a fourth data field for an auxiliary code having a task designation; and

a fifth data field for a data word.

43. The integrated circuit of claim 42, wherein the data distributor is further capable of decoding the plurality of fields and directing the data word to the memory or to the hardware task manager.

44. The integrated circuit of claim 36, wherein the hardware task manager is further capable of producing a task queue for execution by the adaptive execution unit.

45. The integrated circuit of claim 36, wherein the data selector is further capable of providing routing information for the output data packet to an input multiplexer, to an output multiplexer, or to a real time data network.

46. The integrated circuit of claim 36, wherein the data selector is further capable of arbitrating among a plurality of requests from the hardware task manager, the adaptive execution unit, the memory and a direct memory access engine for loading the output data packet into the output pipeline register.

47. The integrated circuit of claim 36, wherein the hardware task manager is embodied as a finite state machine.

48. The integrated circuit of claim 36, wherein the hardware task manager is capable of maintaining a port translation table, generating a plurality of addresses for point-to-point data delivery, providing data flow control, and maintaining a state table for a plurality of tasks.

49. The integrated circuit of claim 48, wherein for each task of a plurality of tasks, the state table comprises a GO bit, a state bit for the task, an input port count, and an output port count.

50. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; and

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for performance of a first algorithmic element of a plurality of algorithmic elements in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for performance of a second algorithmic element of the plurality of algorithmic elements in response to second configuration information, the first algorithmic element being different than the second algorithmic element.

51. The adaptive computing integrated circuit of claim 50, wherein the plurality of algorithmic elements comprises at least two of the following algorithmic elements:

a radix-2 Fast Fourier Transformation (FFT), a radix-4 Fast Fourier Transformation (FFT), a one-dimensional Discrete Cosine Transformation (DCT), a multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, convolutional encoding, scrambling, puncturing, interleaving, modulation mapping, Golay correlation, OVSF code generation, Haddamard Transformation, Turbo Decoding, bit correlation, Griffiths LMS algorithm, variable length encoding, uplink scrambling code generation, downlink scrambling code generation, downlink despreading, uplink spreading, uplink concatenation, Viterbi encoding, Viterbi decoding, cyclic redundancy coding (CRC), complex multiplication, data compression, motion compensation, channel searching, channel acquisition, and multipath correlation.

52. The adaptive computing integrated circuit of claim 50, wherein performance of each algorithmic element, of the plurality of algorithmic elements comprises a simultaneous performance of a plurality of operations.

53. The adaptive computing integrated circuit of claim 52, wherein the plurality of operations comprises at least two of the following operations:

move, input, output, add, subtract, multiply, complex multiply, divide, shift, and multiply and accumulate (MAC).

54. The adaptive computing integrated circuit of claim 50, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures comprising at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, synchronization, queuing, over sampling, under sampling, adaptation, configuration, reconfiguration, control, input, output, and field programmability.

55. The adaptive computing integrated circuit of claim 50, wherein the interconnection network is capable of routing data and control information between and among the plurality of heterogeneous computational elements.

56. The adaptive computing integrated circuit of claim 50, further comprising:

a controller coupled to the plurality of heterogeneous computational elements and to the interconnection network, the controller capable of directing and scheduling the configuration of the plurality of heterogeneous computational elements for performance of the first algorithmic element and the reconfiguration of the plurality of heterogeneous computational elements for performance of the second algorithmic element.

57. The adaptive computing integrated circuit of claim 56, wherein the controller is an adaptive finite state machine comprised of a second plurality of heterogeneous computational elements configured for control processing through a second interconnection network.

58. The adaptive computing integrated circuit of claim 56, wherein the controller is capable of controlling power distribution to the plurality of heterogeneous computational elements and the interconnection network.

59. The adaptive computing integrated circuit of claim 50, further comprising:

a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory capable of storing the first configuration information and the second configuration information.

60. The adaptive computing integrated circuit of claim 59, wherein the memory is an adaptive memory comprised of a second plurality of computational elements configured for memory functionality through a second interconnection network.

61. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, the first functional mode being different than the second functional mode; and

a fixed function node coupled to the interconnection network, the fixed function node having a third fixed architecture, the fixed function node capable of performing a predetermined application.

62. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is not configurable and is not reconfigurable.

63. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is capable of parameter adjustment for performance of the predetermined application, the parameter adjustment comprising changing one or more of the following parameters:

a number of filter coefficients, a number of parallel input bits, a number of parallel output bits, a number of selected points for Fast Fourier Transformation, a number of bits of precision, a code rate, a number of bits of interpolation of a trigonometric function, and real or complex number valuation.

64. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a microprocessor.

65. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a digital signal processor.

66. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a co-processor.

67. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a cascaded integrated comb (CIC) filter.

68. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a parameterized, cascaded integrated comb (CIC) filter.

69. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a finite impulse response (FIR) filter.

70. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a finite impulse response (FIR) filter parameterized for variable filter length.

71. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a processor having an embedded operating system.

72. The adaptive computing integrated circuit of claim 61, wherein the fixed function node is a controller capable of directing and scheduling the configuration of the plurality of heterogeneous computational elements for the first functional mode and the reconfiguration of the plurality of heterogeneous computational elements for the second functional mode.

73. The adaptive computing integrated circuit of claim 61, further comprising:

a memory coupled to the plurality of heterogeneous computational elements and to the interconnection network, the memory operative to store the first configuration information and the second configuration information.

74. A method for adaptive computing, the comprising:

in response to first configuration information, configuring through an interconnection network a plurality of heterogeneous computational elements for performance of a first algorithmic element of a plurality of algorithmic elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture; and

in response to second configuration information, reconfiguring through the interconnection network the plurality of heterogeneous computational elements for performance of a second algorithmic element of the plurality of algorithmic elements, the first algorithmic element being different than the second algorithmic element.

75. The adaptive computing method of claim 74, wherein the plurality of algorithmic elements comprises at least two of the following algorithmic elements:

a radix-2 Fast Fourier Transformation (FFT), a radix-4 Fast Fourier Transformation (FFT), a one-dimensional Discrete Cosine Transformation (DCT), a multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, convolutional encoding, scrambling, puncturing, interleaving, modulation mapping, Golay correlation, OVSF code generation, Haddamard Transformation, Turbo Decoding, bit correlation, Griffiths LMS algorithm, variable length encoding, uplink scrambling code generation, downlink scrambling code generation, downlink despreading, uplink spreading, uplink concatenation, Viterbi encoding, Viterbi decoding, cyclic redundancy coding (CRC), complex multiplication, data compression, motion compensation, channel searching, channel acquisition, and multipath correlation.

76. The adaptive computing method of claim 74, wherein performance of each algorithmic element, of the plurality of algorithmic elements comprises a simultaneous performance of a plurality of operations.

77. The adaptive computing method of claim 76, wherein the plurality of operations comprises at least two of the following operations:

move, add, subtract, multiply, divide, shift, and multiply and accumulate (MAC).

78. The adaptive computing method of claim 74, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures comprising at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, synchronization, queuing, over sampling, under sampling, adaptation, configuration, reconfiguration, control, input, output, and field programmability.

79. The adaptive computing method of claim 74, further comprising:

reconfigurably routing data and control information through the interconnection network to the plurality of heterogeneous computational elements.

80. The adaptive computing method of claim 74, further comprising:

directing and scheduling the configuration of the plurality of heterogeneous computational elements for performance of the first algorithmic element and the reconfiguration of the plurality of heterogeneous computational elements for performance of the second algorithmic element.

81. The adaptive computing method of claim 74, further comprising:

generating a plurality of control bits;

in response to the plurality of control bits, select an input line from the interconnection network for the reception of input information; and

in response to the plurality of control bits, selecting an output line from the interconnection network for the transfer of output information.

82. An integrated circuit comprising:

an input pipeline register to receive an input data packet;

a memory capable of storing the input data packet;

a hardware task manager capable of processing a plurality of tasks and determining that a first task from the plurality of tasks is capable of being performed and that a second task from the plurality of tasks is capable of being performed, the first task being different than the second task;

a data distributor coupled to the input pipeline register, to the memory, and to the hardware task manager, the data distributor capable of distributing the input data packet to the hardware task manager and further capable of distributing the input data packet to the memory;

an adaptive execution unit coupled to the hardware task manager and to the memory, the adaptive execution unit comprising a plurality of computational elements and a plurality of switching elements coupled to the plurality of computational elements, wherein a first computational element of the plurality of computational elements has a first fixed architecture and a second computational element of the plurality of computational elements has a second fixed architecture, the first fixed architecture being different from the second fixed architecture;

wherein the plurality of switching elements are capable of configuring the plurality of computational elements for performance of the first task in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of the second task in response to second configuration information; and

wherein the plurality of computational elements are further capable of using the input data packet and generating an output data packet from the performance of the first task and the second task;

a data selector coupled to the hardware task manager, to the adaptive execution unit and to the memory, the data selector capable of determining routing for the output data packet; and

an output pipeline register coupled to the data selector to receive the output data packet.

83. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture of a plurality of fixed architectures and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture of the plurality of fixed architectures, the first fixed architecture being different than the second fixed architecture, the plurality of fixed architectures comprising at least two of the following corresponding functions;

memory, addition, multiplication, complex multiplication, subtraction, synchronization, queuing, over sampling, under sampling, adaptation, configuration, reconfiguration, control, input, output, and field programmability;

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for performance of a first algorithmic element of a plurality of algorithmic elements in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for performance of a second algorithmic element of the plurality of algorithmic elements in response to second configuration information, the first algorithmic element being different than the second algorithmic element; and

wherein the plurality of algorithmic elements comprises at least two of the following algorithmic elements;

a radix-2 Fast Fourier Transformation (FFT), a radix-4 Fast Fourier Transformation (FFT), a one-dimensional Discrete Cosine Transformation (DCT), a multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, convolutional encoding, scrambling, puncturing, interleaving, modulation mapping, Golay correlation, OVSF code generation, Haddamard Transformation, Turbo Decoding, bit correlation, Griffiths LMS algorithm, variable length encoding, uplink scrambling code generation, downlink scrambling code generation, downlink despreading, uplink spreading, uplink concatenation, Viterbi encoding, Viterbi decoding, cyclic redundancy coding (CRC), complex multiplication, data compression, motion compensation, channel searching, channel acquisition, multipath correlation.