Semiconductor display device and manufacturing method method thereof

• US 20030155594A1
• Filed: 03/11/2003
• Published: 08/21/2003
• Est. Priority Date: 09/22/2000
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto
• Granted Patent: US 6,909,117 B2
• Time in Patent Office: Days
• US Class Current: 257/291
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A semiconductor display device which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled. Therefore, the GOLD structure TFT having both the hot carrier resistance and the off-current suppressing effect can be formed and the simplification of a manufacturing process of the semiconductor display device and the improvement of performance thereof are compatible with each other.

Claims

1. A semiconductor device comprising a plurality of thin film transistors formed on a transparent insulating substrate, each of said thin film transistors comprising:

a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode,

wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer to gate electrode is formed to have a longer size in a channel direction than the second layer gate electrode,

wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode,

wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate electrode, and

wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the third impurity region.

2. A device according to claim 1, wherein the first impurity region, the second impurity region, and the third impurity region are the same conductivity type impurity regions and have one of an n-type and a p-type as a conductivity type.

3. A device according to claim 1, wherein the first layer gate electrode and the second layer gate electrode comprise different high melting metals.

4. A device according to claim 1, wherein the first layer gate electrode comprises a TaN film as a compound containing high melting metal and the second layer gate electrode comprises a W film as the high melting metal.

5. A device according to claim 1, wherein the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

6. An electronic equipment having a device according to claim 1, wherein the electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.

7. A semiconductor device comprising a plurality of n-channel thin film transistors formed on a transparent insulating substrate, each of the n-channel thin film transistors comprising:

a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode,

wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer gate electrode is formed to have a loneer size in a channel direction than the second layer gate electrode,

wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode,

wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate electrode, and

wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the third impurity region.

8. A device according to claim 7, wherein the first impurity region, the second impurity region, and the third impurity region are n-type impurity regions.

9. A device according to claim 7, wherein an n-type impurity concentration of the first impurity region is 2×

10¹⁶ to 2.7×

10¹⁹ atoms/cm³, preferably, about 1×

10¹⁷ to 5.3×

10¹⁸ atoms/cm³.

10. A device according to claim 7, wherein an n-type impurity concentration of the second impurity region is 4.7×

10¹⁵ to 2.7×

10¹⁸ atoms/cm³, preferably, about 4.7×

10¹⁷ to 5.3×

10¹⁷ atoms/cm³.

11. A device according to claim 7, wherein an n-type impurity concentration of the third impurity region is about 3×

10¹⁸ to 5×

10²¹ atoms/cm³, preferably, about 1.7×

10¹⁹ to 2.7×

10²⁰ atoms/cm³.

12. A device according to claim 7, wherein the first layer gate electrode and the second layer gate electrode comprise different high melting metals.

13. A device according to claim 7, wherein the first layer gate electrode comprises a TaN film as a compound containing high melting metal and the second layer gate electrode comprises a W film as the high melting metal.

14. A device according to claim 7, wherein the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

15. An electronic equipment having a device according to claim 7, wherein the electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted displays a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.

16. A method of manufacturing a semiconductor device comprising:

laminating a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film over a transparent insulating substrate in order from a side near the transparent insulating substrate;

forming a resist pattern for gate electrode formation over the substrate with the laminated structure;

performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode;

ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode;

performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode;

performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignment;

ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode;

removing the negative resist pattern; and

ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode.

17. A method according to claim 16, wherein a dose of the second impurity region is set to be lower than that of the first impurity region and higher than that of the third impurity region.

18. A method according to claim 16, wherein the impurity is ion-implanted by an ion dope apparatus.

19. A method according to claim 16, wherein respective impurity concentrations of the second impurity region and the third impurity region are independently controlled.

20. A method according to claim 16, wherein different kinds of high melting metals or different compounds containing the high melting metals are applied to the first layer gate electrode film and the second layer gate electrode film.

21. A method according to claim 16, wherein a TaN film as a compound containing high melting metal is applied to the first layer gate electrode film and a W film as the high melting metal is applied to the second layer gate electrode film.

22. A method according to claim 16, wherein the semiconductor layer is formed with one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

23. A method according to claim 16, wherein the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.

24. A method of manufacturing a semiconductor device comprising:

forming a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film on a transparent insulating substrate in order from a side near the transparent insulating substrate;

forming a resist pattern for gate electrode formation on the substrate with a resultant structure;

performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode;

ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode;

performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode;

ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode;

performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignmnent; and

ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode.

25. A method according to claim 24, wherein a dose of the third impurity region is set to be lower than that of the first impurity region and higher than that of the second impurity region.

26. A method according to claim 24, wherein the impurity is ion-implanted by an ion dope apparatus.

27. A method according to claim 24, wherein respective impurity concentrations of the second impurity region and the third impurity region are independently controlled.

28. A method according to claim 24, wherein different kinds of high melting metals or different compounds containing the high melting metals are applied to the first layer gate electrode film and the second layer gate electrode film.

29. A method according to claim 24, wherein a TaN film as a compound containing high melting metal is applied to the first layer gate electrode film and a W film as the high melting metal is applied to the second layer gate electrode film.

30. A method according to claim 24, wherein the semiconductor layer is formed with one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

31. A method according to claim 24, wherein the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.

32. A method of manufacturing a semiconductor device comprising:

forming a semiconductor layer over a substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer;

forming a negative resist over the substrate;

performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment;

introducing an impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks;

removing the negative resist pattern; and

introducing the impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask.

33. A method according to claim 32, wherein an impurity concentration of the second impurity regions in the semiconductor layer is lower than that of the first impurity regions.

34. A method according to claim 32, wherein the impurity is ion-implanted by an ion dope apparatus.

35. A method according to claim 32, wherein different kinds of high melting metals or different compounds containing the high melting metals are applied to the first conductive layer and the second conductive layer.

36. A method according to claim 32, wherein the first conductive layer comprises TaN and the second conductive layer comprises W.

37. A method according to claim 32, wherein the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

38. A method according to claim 32, wherein the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.

39. A method of manufacturing a semiconductor device comprising:

forming a semiconductor layer over a substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer;

introducing an impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask;

forming a negative resist over the substrate;

performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment; and

introducing the impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks.

40. A method according to claim 39, wherein an impurity concentration of the second impurity regions in the semiconductor layer is lower than that of the first impurity regions.

41. A method according to claim 39, wherein the impurity is ion-implanted by an ion dope apparatus.

42. A method according to claim 39, wherein different kinds of high melting metals or different compounds containing the high melting metals are applied to the first conductive layer and the second conductive layer.

43. A method according to claim 39, wherein the first conductive layer comprises TaN and the second conductive layer comprises W.

44. A method according to claim 39, wherein the semiconductor layer comprises one of a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.

45. A method according to claim 39, wherein the semiconductor device is included in an electronic equipment is selected from the group consisting of a video camera, a digital camera, a rear type projector, a front type projector, a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, a mobile computer, a mobile telephone, an electronic book, a personal computer, and a recording medium.