Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system

• US 20030160641A1
• Filed: 05/03/2002
• Published: 08/28/2003
• Est. Priority Date: 05/06/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chang, Wanli, Starr, Gregory W.
• Granted Patent: US 6,798,302 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1803 the counter or frequency divider being connected to a cycle or pulse swallowing circuit
• CPC Class Codes: H03M 1/808 using resistors
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Claims

1. A phase locked loop circuit comprising:

a signal generator; and

a spread spectrum modulator coupled to the signal generator, wherein the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage.

2. The phase locked loop circuit of claim 1, wherein the spread spectrum modulator comprises at least one selector, wherein the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

3. The phase locked loop circuit of claim 2, wherein the at least one selector selects a high voltage, a low voltage, and a reference voltage for the spread spectrum modulator.

4. The phase locked loop circuit of claim 3, wherein the at least one selector selects the high voltage, the low voltage, and the reference voltage for the spread spectrum modulator in user mode.

5. The phase locked loop circuit of claim 3, wherein the spread spectrum modulator comprises a voltage divider coupled to the at least one selector, the at least one selector comprising a plurality of multiplexers, the voltage divider comprising a plurality of resistors coupled in series, wherein a first plurality of nodes from the voltage divider are coupled to a first multiplexer of said plurality of multiplexers, a second plurality of nodes from voltage divider are coupled to a second multiplexer of said plurality of multiplexers, and a third plurality of nodes from the voltage divider are coupled to a third multiplexer of said plurality of multiplexers, further wherein the first, second, and third multiplexers output the high voltage, the low voltage, and the reference voltage respectively.

6. The phase locked loop circuit of claim 5, wherein the spread spectrum modulator comprises:

a buffer coupled to the voltage divider;

a waveform generator coupled to the plurality of multiplexers;

a voltage adder coupled to the plurality of multiplexers and the buffer; and

a voltage subtracter coupled to the voltage adder and the waveform generator.

7. The phase locked loop circuit of claim 6, wherein the waveform generator comprises:

a first comparator, wherein the first comparator compares a voltage at an output node of the waveform generator with the high voltage;

a second comparator, wherein the second comparator compares the voltage at the output node with the low voltage;

a flip-flop coupled to the first and second comparators;

a first switch coupled to a first output node of the flip-flop; and

a second switch coupled to a second output node of the flip-flop;

a first current source coupled to the first switch, the first current source for increasing current at the output node; and

a second current source coupled to the second switch, the second current source for sinking current from the output node.

8. The phase locked loop circuit of claim 7, wherein the waveform generator is programmable to provide different spread rates.

9. The phase locked loop circuit of claim 7, wherein the voltage adder comprises an operational amplifier, wherein the voltage adder receives the reference voltage and an output of the buffer at a positive input node and provides a voltage adder output that is a sum of the reference voltage and the output of the buffer.

10. The phase locked loop circuit of claim 9, wherein the voltage subtracter comprises an operational amplifier, wherein the voltage subtracter subtracts the voltage at the output node of the waveform generator from the voltage adder output.

11. The phase locked loop of claim 1 further comprising:

a detector;

a charge pump filter coupled to the detector and the spread spectrum modulator;

a loop filter coupled to the charge pump and the spread spectrum modulator;

a first divider coupled to the signal generator and a first input node of the detector, wherein the first divider receives a signal generator output signal from the signal generator and provides a first input signal to the first input node of the detector;

a second divider coupled to a second input node of the detector;

a third divider coupled to the signal generator; and

wherein the second divider receives a reference clock signal and provides a second input signal to the second input node of the detector, further wherein the third divider receives the signal generator output signal from the signal generator and provides an output clock signal.

12. The phase locked loop circuit of claim 1, wherein the spread spectrum modulator comprises a waveform generator.

13. The phase locked loop circuit of claim 12, wherein the waveform generator comprises:

a first comparator, wherein the first comparator compares a voltage at an output node of the waveform generator with a high voltage;

a second comparator, wherein the second comparator compares the voltage at the output node with a low voltage;

a flip-flop coupled to the first and second comparators;

a first switch coupled to a first output node of the flip-flop; and

a second switch coupled to a second output node of the flip-flop;

a first current source coupled to the first switch, the first current source for increasing current at the output node; and

a second current source coupled to the second switch, the second current source for sinking current from the output node.

14. The phase locked loop circuit of claim 12, wherein the spread spectrum modulator further comprises:

a voltage subtracter coupled to the waveform generator; and

a voltage adder coupled to the voltage subtracter.

15. A digital system including a programmable logic device and the phase locked loop circuit of claim 1.

16. A programmable logic device including the phase locked loop circuit of claim 1.

17. A phase locked loop circuit comprising a spread spectrum modulator, the spread spectrum modulator comprising a voltage divider and a selector coupled to the voltage divider, wherein the selector selects a plurality of voltages that correspond to a spread rate and percentage of spread for the spread spectrum modulator.

18. The phase locked loop circuit of claim 17, wherein the selector comprises a plurality of multiplexers, wherein a first multiplexer of the plurality of multiplexers selects a high voltage, a second multiplexer of the plurality of multiplexers selects a low voltage, and a third multiplexer of the plurality of multiplexers selects a reference voltage.

19. The phase locked loop circuit of claim 18, wherein the voltage divider comprises a plurality of resistors coupled in series.

20. The phase locked loop circuit of claim 19, wherein the spread spectrum modulator further comprises:

a buffer coupled to the voltage divider;

a waveform generator coupled to the selector, wherein the waveform generator receives the high voltage and low voltage as an input and provides a waveform generator output at a waveform generator output node;

a voltage adder coupled to the buffer and the selector, wherein the voltage adder receives the reference voltage from the selector and a buffered version of a control voltage from the buffer, further wherein the voltage adder provides a voltage adder output voltage that is a sum of the reference voltage and the buffered version of the control voltage;

a voltage subtracter coupled to the waveform generator, wherein the voltage subtracter receives the waveform generator output and the voltage adder output, subtracts the waveform generator output from the voltage adder output, and provides a spread spectrum control voltage as an output.

21. The phase locked loop circuit of claim 20, wherein the waveform generator comprises:

a first comparator, wherein the first comparator compares the waveform generator output with the high voltage;

a second comparator, wherein the second comparator compares the waveform generator output with the low voltage;

a flip-flip coupled to the first and second comparators;

a first switch coupled to a first output node of the flip-flop; and

a second switch coupled to a second output node of the flip-flop;

wherein the first switch is coupled to a first current source for increasing current at the waveform generator output node, and wherein the second switch is coupled to a second current source for sinking current from the waveform generator output node.

22. The phase locked loop circuit of claim 21, wherein the voltage adder comprises an operational amplifier, wherein the voltage adder receives the reference voltage and an output of the buffer at a noninverting input terminal, further wherein the voltage subtracter comprises an operational amplifier, wherein the voltage subtracter receives the waveform generator output at an inverting input terminal and the voltage adder output at a noninverting input terminal.

23. The phase locked loop of claim 20 further comprising:

a detector;

a charge pump filter coupled to the detector and the spread spectrum modulator;

a loop filter coupled to the charge pump and the spread spectrum modulator;

a first divider coupled to the signal generator and a first input node of the detector, wherein the first divider receives a signal generator output signal from the signal generator and provides a first input signal to the first input node of the detector;

a second divider coupled to a second input node of the detector;

a third divider coupled to the signal generator; and

wherein the second divider receives a reference clock signal and provides a second input signal to the second input node of the detector, further wherein the third divider receives the signal generator output signal from the signal generator and provides an output clock signal.

24. A digital system including a programmable logic device and the phase locked loop circuit of claim 20.

25. A programmable logic device including the phase locked loop circuit of claim 20.

26. A method of providing an output clock signal, the method comprising:

spreading a control voltage utilizing an analog voltage controlled spread spectrum modulator to provide a spread spectrum control voltage; and

generating an output clock signal in response to the spread spectrum control voltage.

27. The method of claim 26, wherein the spreading comprises:

dividing the control voltage to provide a plurality of voltage levels;

selecting a high voltage, a low voltage, and a reference voltage from the plurality of voltage levels;

generating a voltage waveform in response to the high voltage and the low voltage;

adding the reference voltage with a buffered version of the control voltage to provide a sum voltage; and

subtracting the voltage waveform from the sum voltage to provide the spread spectrum control voltage.

28. The method of claim 27 further comprising:

comparing a feedback clock signal with a reference clock signal to provide the control voltage.

29. The method of claim 26, wherein the spreading comprises:

generating a voltage waveform in response to a high voltage and a low voltage;

adding a reference voltage with the control voltage to provide a sum voltage; and

subtracting the voltage waveform from the sum voltage to provide the spread spectrum control voltage.

30. A phase locked loop comprising:

means for spreading a control voltage, wherein said means for spreading uses analog voltage controlled spread spectrum modulation and provides a spread spectrum control voltage; and

means for generating an output clock signal, wherein the means for generating generates the output clock signal in response to the spread spectrum control voltage.

31. The phase locked loop of claim 30, wherein the means for spreading comprises:

means for dividing the control voltage to provide a plurality of voltage levels;

means for selecting coupled to the means for dividing, wherein the means for selecting selects a high voltage, a low voltage, and a reference voltage from the plurality of voltage levels;

means for generating a voltage waveform coupled to the means for selecting, wherein the means for generating a voltage waveform generates a voltage waveform in response to the high voltage and the low voltage;

means for adding coupled to the means for selecting, wherein the means for adding adds the reference voltage with a buffered version of the control voltage to provide a sum voltage; and

means for subtracting coupled to the means for adding and the means for generating a voltage waveform, wherein the means for subtracting subtracts the voltage waveform from the sum voltage to provide the spread spectrum control voltage.

32. The phase locked loop of claim 31 further comprising means for comparing coupled to the means for generating and the means for spreading, wherein the means for comparing compares a feedback clock signal with a reference clock signal, wherein the means for comparing provides the control voltage.

33. The phase locked loop of claim 30, wherein the means for spreading comprises:

means for generating a voltage waveform, wherein the means for generating a voltage waveform generates a voltage waveform in response to a high voltage and a low voltage;

means for adding, wherein the means for adding adds a reference voltage with the control voltage to provide a sum voltage; and

means for subtracting coupled to the means for adding and the means for generating a voltage waveform, wherein the means for subtracting subtracts the voltage waveform from the sum voltage to provide the spread spectrum control voltage.