Substrate mapping

• US 20030162311A1
• Filed: 04/25/2003
• Published: 08/28/2003
• Est. Priority Date: 08/22/2001
• Status: Active Grant

• Current Assignee: Derek J. Gochnour, Warren M. Farnworth
• Original Assignee: Derek J. Gochnour, Warren M. Farnworth
• Inventors: Farnworth, Warren M., Gochnour, Derek J.
• Granted Patent: US 6,808,947 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/53043 including means to divert defective work part
• CPC Class Codes: Y10T 29/53178 Chip component
• CPC Class Codes: Y10T 29/53187 Multiple station assembly apparatus

Abstract

A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.

Claims

1. An assembly method for attaching a semiconductor die and a substrate having a plurality of die attach sites on a surface thereof comprising:

mapping said plurality of die attach sites on said mounting substrate;

determining good die attach sites and defective die attach sites on said substrate;

storing said information in an electronic file; and

attaching at least one semiconductor die to said mounting substrate using said information by one of attaching a known good die to a good die attach site of said good die attach sites and attaching a known defective die to a defective die attach site of said defective die attach sites.

2. The method of claim 1, wherein said mapping comprises testing at least one die attach site of said plurality of die attach sites on said mounting substrate.

3. The method of claim 1, further comprising providing a designator having substrate identification information on a peripheral portion of said mounting substrate.

4. The method of claim 3, further comprising providing a reading unit for reading said designator to access said mapped information in said electronic file with respect to said mounting substrate corresponding to said substrate identification information.

5. A method for fabricating semiconductor packages, each package having a mounting substrate having a plurality of die attach sites on at least one surface thereof, the method comprising:

evaluating said plurality of die attach sites on said mounting substrate for determining information regarding said die attach site;

determining good die attach sites and defective die attach sites from said information;

attaching at least one semiconductor die to said mounting substrate according to said information by one of attaching a known good die to a good die attach site of said good die attach sites and attaching a known defective die to a defective die attach site of said defective die attach sites; and

encapsulating said mounting substrate using an encapsulation material.

6. The method of claim 5, wherein said evaluating comprises testing each of said plurality of die attach sites on said mounting substrate.

7. The method of claim 5, further comprising providing said mapped information to an electronic file.

8. The method of claim 7, further comprising providing a designator having substrate identification information on a peripheral portion of said mounting substrate.

9. The method of claim 8, further comprising reading said designator with a reading unit to access said mapped information in said electronic file with respect to said mounting substrate corresponding to said substrate identification information.

10. The method of claim 5, further comprising segregating said at least one semiconductor die attached to said mounting substrate into a semiconductor die package.

11. The method of claim 10, wherein said segregating comprises separating from said semiconductor package at least one semiconductor die package having one of said known good die attached to said good die attach site and said known defective die attached to said defective die attach site according to said mapped information.

12. The method of claim 5, wherein said encapsulating comprises transfer molding said mounting substrate.