Diverse band gap energy level semiconductor device

• US 20030164492A1
• Filed: 09/25/2002
• Published: 09/04/2003
• Est. Priority Date: 02/15/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H.
• Granted Patent: US 7,049,678 B2
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Claims

1. A semiconductor device comprising:

a first semiconductor layer having a first band gap energy level;

a second semiconductor layer having a second band gap energy level, wherein the second band gap energy level is different from the first band gap energy level; and

an insulating layer disposed between the first and second layers that is capable of being selectively breached by passing a current between one of the first and second semiconductor layers.

2. The device of claim 1 wherein the first semiconductor layer comprises silicon.

3. The device of claim 1 wherein the second semiconductor layer comprises silicon carbide.

4. The device of claim 2 wherein the second semiconductor layer comprises silicon carbide.

5. The device of claim 1 wherein the first semiconductor layer comprises silicon-germanium.

6. The device of claim 2 wherein the second semiconductor layer comprises silicon-germanium.

7. The device of claim 2 wherein the second semiconductor layer comprises gallium arsenide.

8. The device of claim 2 wherein the second semiconductor layer comprises indium phosphide.

9. The device of claim 1 wherein the first semiconductor layer is selected from the group consisting of:

silicon, silicon-germanium, and indium phosphide.

10. The device of claim 1 wherein the second semiconductor layer is selected from the group consisting of:

silicon, silicon carbide, and gallium arsenide.

11. The device of claim 9 wherein the second semiconductor layer is selected from the group consisting of:

silicon carbide and gallium arsenide.

12. The device of claim 1 wherein the insulating layer comprises silicon dioxide.

13. A memory element comprising:

an insulating layer capable of being selectively breached by passing a current therethrough; and

a first semiconductor layer in electrical communication with the-insulating layer having a first band gap energy level, and

a second semiconductor layer adjacent the first semiconductor layer and having a second band gap energy level, wherein the second band gap energy level is different from the first band gap energy level.

14. The memory element of claim 13 further comprising an input terminal in electrical communication with the second semiconductor element.

15. The memory element of claim 13 further comprising an output terminal in electrical communication with the insulating layer.

16. The memory element of claim 14 further comprising an output terminal in electrical communication with the insulating layer.

17. The memory element of claim 16 wherein the output terminal, insulating layer, first semiconductor, second semiconductor, and input terminal comprise a vertically oriented pillar arrangement.

18. The memory element of claim 13 wherein the first semiconductor layer comprises silicon.

19. The memory element of claim 13 wherein the second semiconductor layer comprises silicon carbide.

20. The memory element of claim 18 wherein the second semiconductor layer comprises silicon carbide.

21. The memory element of claim 13 wherein the second semiconductor layer comprises silicon-germanium.

22. The memory element of claim 18 wherein the second semiconductor layer comprises gallium arsenide.

23. The memory element of claim 18 wherein the second semiconductor layer comprises indium phosphide.

24. The memory element of claim 13 wherein the first semiconductor layer is selected from the group consisting of:

silicon, silicon-germanium, and indium phosphide.

25. The device of claim 13 wherein the second semiconductor layer is selected from the group consisting of:

silicon, silicon carbide, and gallium arsenide.

26. The device of claim 24 wherein the second semiconductor layer is selected from the group consisting of:

silicon carbide and gallium arsenide.

27. The device of claim 13 wherein the insulating layer comprises silicon dioxide.

28. A memory cell comprising:

a rail-stack structure having;

(a) a first rail-stack comprising;

(1) a first conductor layer; and

(2) at least one semiconductor layer having a first band gap energy level;

(b) a second rail-stack in electrical communication with the first rail-stack and comprising;

(1) a second conductor layer;

(2) at least one semiconductor layer having a second band gap energy, wherein the second band gap energy level is different from the first band gap energy level; and

(3) an insulating layer capable of being selectively breached by passing a current from one of the first and second rail-stacks.

29. The memory element of claim 28 wherein the first semiconductor layer comprises silicon.

30. The memory element of claim 28 wherein the second semiconductor layer comprises silicon carbide.

31. The memory element of claim 29 wherein the second semiconductor layer comprises silicon carbide.

32. The memory element of claim 28 wherein the second semiconductor layer comprises silicon-germanium.

33. The memory element of claim 29 wherein the second semiconductor layer comprises gallium arsenide.

34. The memory element of claim 29 wherein the second semiconductor layer comprises indium phosphide.

35. The memory element of claim 28 wherein the first semiconductor layer is selected from the group consisting of:

silicon, silicon-germanium, and indium phosphide.

36. The device of claim 28 wherein the second semiconductor layer is selected from the group consisting of:

silicon, silicon carbide, and gallium arsenide.

37. The device of claim 35 wherein the second semiconductor layer is selected from the group consisting of:

silicon carbide and gallium arsenide.

38. The device of claim 28 wherein the insulating layer comprises silicon dioxide.

39. A semiconductor structure comprising:

a first semiconductor having a first band gap energy level;

a second semiconductor in electrical communication with the first semiconductor and having a second band gap energy level, wherein the second band gap energy level is different from the first band gap energy level;

a wordline input electrical communication with the first semiconductor; and

a bitline output in electrical communication with the second semiconductor.

40. The semiconductor structure of claim 39 further comprising an insulator layer disposed intermediate the first and second semiconductors.

41. The semiconductor structure of claim 40 wherein the insulator layer is capable of being selectively breached by passing a current between one of the first and second semiconductor layers to form a memory state.

42. A semiconductor structure comprising:

a first conductor and a second conductor;

a steering element in circuit communication with the first conductor and comprising at least first and second semiconductor materials, the first semiconductor material having a first band gap energy level, the second semiconductor in electrical communication with the first semiconductor and having a second band gap energy level, wherein the second band gap energy level is different from the first band gap energy level; and

a state change element in circuit communication with the steering element and the second conductor and comprising a selectable high impedance state and a selectable low impedance state.

43. The semiconductor structure of claim 42 wherein the steering element and state change element are configured in a vertically-oriented pillar arrangement.

44. The semiconductor structure of claim 42 wherein the state change element comprises an insulator layer.

45. The semiconductor structure of claim 44 wherein the insulator layer is capable of being selectively breached by passing a current between one of the first and second conductor layers so as to select the low impedance state.

46. The device of claim 42 wherein the first semiconductor layer comprises silicon.

47. The device of claim 42 wherein the second semiconductor layer comprises silicon carbide.

48. The device of claim 46 wherein the second semiconductor layer comprises silicon carbide.

49. The device of claim 42 wherein the first semiconductor layer comprises silicon-germanium.

50. The device of claim 46 wherein the second semiconductor layer comprises silicon-germanium.

51. The device of claim 46 wherein the second semiconductor layer comprises gallium arsenide.

52. The device of claim 46 wherein the second semiconductor layer comprises indium phosphide.

53. The device of claim 42 wherein the first semiconductor layer is selected from the group consisting of:

silicon, silicon-germanium, and indium phosphide.

54. The device of claim 42 wherein the second semiconductor layer is selected from the group consisting of:

silicon, silicon carbide, and gallium arsenide.

55. The device of claim 53 wherein the second semiconductor layer is selected from the group consisting of:

silicon carbide and gallium arsenide.

56. The device of claim 44 wherein the insulator layer comprises silicon dioxide.