Gigabit Ethernet adapter

• US 20030165160A1
• Filed: 04/23/2002
• Published: 09/04/2003
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Johnson, Michael Ward, Uyeshiro, Robin Yasu, Minami, John Shigeto, Su, Steve
• Granted Patent: US 8,218,555 B2
• Time in Patent Office: Days
• US Class Current: 370/466
• CPC Class Codes: H04L 47/12 Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 47/27 Evaluation or update of window size, e.g. using information derived from acknowledged [ACK] packets
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 47/6275 based on priority
• CPC Class Codes: H04L 67/04 specially adapted for terminals or networks with limited capabilities; specially adapted for terminal portability
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/085 specially adapted for interworking of IP-based networks with other networks
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A gigabit Ethernet adapter provides a provides a low-cost, low-power, easily manufacturable, small form-factor network access module which has a low memory demand and provides a highly efficient protocol decode. The invention comprises a hardware-integrated system that both decodes multiple network protocols in a byte-streaming manner concurrently and processes packet data in one pass, thereby reducing system memory and form factor requirements, while also eliminating software CPU overhead. A preferred embodiment of the invention comprises a plurality of protocol state machines that decode network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, Raw Socket, RARP, ICMP, IGMP, iSCSI, RDMA, and FCIP concurrently as each byte is received. Each protocol handler parses, interprets, and strips header information immediately from the packet, requiring no intermediate memory. The invention provides an Internet tuner core, peripherals, and external interfaces. A network stack processes, generates and receives network packets. An internal programmable processor controls the network stack and handles any other types of ICMP packets, IGMP packets, or packets corresponding to other protocols not supported directly by dedicated hardware. A virtual memory manager is implemented in optimized, hardwired logic. The virtual memory manager allows the use of a virtual number of network connections which is limited only by the amount of internal and external memory available.

Claims

1. An apparatus for decoding and encoding network protocols and processing data, comprising:

a network stack for receiving and transmitting packets and for encoding and decoding packets;

a plurality of dedicated hardwired logic protocol modules;

wherein each protocol module is optimized for a specific network protocol; and

wherein said protocol modules execute in parallel.

2. The apparatus of claim 1, further comprising:

an internal programmable processor; and

wherein said internal processor controls said network stack.

3. The apparatus of claim 2, wherein other types of packets corresponding to other protocols not supported directly by dedicated hardware are processed by said internal processor.

4. The apparatus of claim 1, wherein said protocol modules include a TCP protocol module.

5. The apparatus of claim 4, wherein said TCP module processes TCP and UDP network traffic.

6. The apparatus of claim 4, wherein said TCP module supports a virtual number of connections by using memory management hardware.

7. The apparatus of claim 4, wherein said TCP module supports the reassembly of out-of-order packets using either an internal processor or dedicated hardwired logic.

8. The apparatus of claim 4, wherein said TCP module supports the TCP protection against wrapped sequence numbers (PAWS) using dedicated and optimized hardwired logic

9. The apparatus of claim 4, wherein said TCP module supports TCP keep-alive timers using dedicated and optimized hardwired logic

10. The apparatus of claim 4, wherein said TCP module supports TCP slow start algorithm.

11. The apparatus of claim 4, wherein said TCP module supports TCP fast-retransmission algorithm and fast-recovery algorithm.

12. The apparatus of claim 4, wherein said TCP module supports TCP Nagle algorithm using either an internal processor or dedicated hardwired logic.

13. The apparatus of claim 4, wherein said TCP module supports TCP selective-acknowledgement (SACK) option.

14. The apparatus of claim 4, wherein said TCP module measures packet round-trip times.

15. The apparatus of claim 4, wherein said TCP module performs congestion-avoidance algorithms.

16. The apparatus of claim 4, wherein said TCP module supports TCP scaling-window using dedicated and optimized hardwired logic.

17. The apparatus of claim 4, wherein said TCP module supports maximum-segment size (MSS) discovery using dedicated and optimized hardwired logic.

18. The apparatus of claim 4, wherein said TCP module supports time-wait assassination using dedicated and optimized hardwired logic.

19. The apparatus of claim 4, wherein said TCP module supports port forwarding using dedicated and optimized hardwired logic.

20. The apparatus of claim 1, further comprising:

an IP router module;

wherein said IP router module performs any of;

default IP routing capabilities including hardware to network address translation;

routing for multiple host IP addresses;

routing for host-specific and network-specific routes;

dynamic update of routing information after receiving an ICMP redirect packet message;

routing with IP broadcast addresses, including, but not limited to;

limited broadcasts, subnet-directed broadcasts, and network-directed broadcasts;

routing with loopback IP addresses; and

routing with IP multicast addresses.

21. The apparatus of claim 1, wherein said protocol modules include an IP protocol module, and wherein said IP module processes, generates, and responds to IP network packets.

22. The apparatus of claim 21, wherein said IP module comprises dedicated and optimized hardwired logic for defragmenting IP network packets.

23. The apparatus of claim 1, wherein said protocol modules include an ICMP module comprising dedicated and optimized hardwired logic for processing, generating, and responding to ICMP or IGMP network messages.

24. The apparatus of claim 1, wherein said protocol modules include an ICMP module consisting of optimized hardwired logic that can be programmed to hand certain ICMP or IGMP functions to an internal or external processor.

25. The apparatus of claim 1, further comprising:

an IP identification generator module that uses dedicated optimized hardwired logic to generate an identification field for IP packets that has a true random distribution and prevents attempts to predict future values of the identification field.

26. The apparatus of claim 1, wherein said protocol modules include virtual a socket module that allows the use of a virtual number of network connections.

27. The apparatus of claim 1, wherein said protocol modules include a receive-state handler module, wherein said receive-state handler module responds to TCP network packets in an automated fashion, including any of:

the generation of reset (RST) packets;

the generation of synchronize with acknowledgement packets (SYN/ACK);

the generation of acknowledgement packets (ACK);

the generation of synchronization packets (SYN);

the generation of finish packets (FIN);

the generation of finish/acknowledgement packets (FIN/ACK); and

the generation of reset/acknowledgement packets (RST/ACK).

28. The apparatus of claim 1, wherein said protocol modules include an ARP protocol module, and wherein said ARP module responds to network ARP requests by generating network ARP replies.

29. The apparatus of claim 28, wherein said ARP module generates any of:

ARP requests in combination with a hardware ARP address cache;

ARP requests for multiple IP addresses;

unicast ARP requests; and

gratuitous ARP requests.

30. The apparatus of claim 28, wherein said ARP module is programmed to hand certain ARP functions to an internal or external processor.

31. The apparatus of claim 28, wherein said ARP module is programmed with varying priorities.

32. The apparatus of claim 28, further comprising:

a cache for ARP addresses constructed using optimized hardwired logic;

wherein said ARP cache uses a dynamically sized table controlled by dedicated hardware;

wherein said ARP cache supports the ability to act as an ARP proxy; and

wherein said ARP cache uses dedicated hardwired logic to control the expiration time of ARP cache entries.

33. The apparatus of claim 1, wherein said protocol modules include an RARP protocol module, and wherein said RARP module can request or supply an IP address.

34. The apparatus of claim 33, wherein said RARP module is programmed to hand certain RARP functions to an internal or external processor.

35. The apparatus of claim 1, further comprising:

a memory structure that permits hardwired virtual memory management;

wherein said memory structure comprises;

a set of different sized control blocks each optimized for their purpose; and

a mechanism to link control blocks using pointers stored in each control block.

36. The apparatus of claim 35, wherein said hardwired virtual memory management allocates control blocks, updates control blocks, and deallocates control blocks.

37. The apparatus of claim 1, further comprising:

a priority queue that schedules packets for transmission according to a programmable priority.

38. The apparatus of claim 1, further comprising:

a sequencer that calculates and assigns priorities for network packets to be processed.

39. The apparatus of claim 1, further comprising:

a memory architecture that stores network information on the state of each network connection in such a manner that it protects against network denial of service attacks.

40. The apparatus of claim 1, wherein said network stack processes, generates and receives TCP and IP packets, and wherein said network stack is programmed to hand certain IP or TCP packet processing functions to an internal or external processor.

41. The apparatus of claim 1, wherein said network stack processes, generates and receives IP packets that encapsulate upper-level protocols such as iSCSI or RDMA.

42. The apparatus of claim 1, further comprising:

a virtual memory manager implemented in hardwired logic.

43. The apparatus of claim 42, wherein said virtual memory manager allows the use of a virtual number of network connections, and wherein said virtual number of network connections is limited only by the amount of internal or external memory available.

44. The apparatus of claim 42, wherein said virtual memory manager uses a hardwired locking mechanism to prevent interference between memory locations.

45. The apparatus of claim 42, wherein said virtual memory manager uses a chain of memory structures to store network connection information in memory.

46. The apparatus of claim 42, wherein said virtual memory manager uses dedicated hardwired circuits to search, update, insert, and delete entries in a linked list or chain of memory structures.

47. The apparatus of claim 42, wherein said virtual memory manager uses several different types of control blocks to store network connection information, depending on the state of the network connection.

48. A process for decoding and encoding network protocols and processing data, comprising the steps of:

providing a network stack for receiving and transmitting packets and for encoding and decoding packets;

providing a plurality of dedicated protocol state machines;

wherein each protocol state machine is optimized for a specific network protocol; and

wherein said protocol state machines execute in parallel.

49. The process of claim 48, further comprising the step of:

providing an internal programmable processor; and

wherein said internal processor controls said network stack.

50. The process of claim 49, wherein other types of packets corresponding to other protocols not supported directly by dedicated hardware are processed by said internal processor.

51. The process of claim 48, wherein said protocol state machines include a TCP protocol state machine.

52. The process of claim 51, wherein said TCP state machine processes TCP and UDP network traffic.

53. The process of claim 51, wherein said TCP state machine supports a virtual number of connections by using memory management hardware.

54. The process of claim 51, wherein said TCP state machine supports the reassembly of out-of-order packets using either an internal processor or dedicated hardwired logic.

55. The process of claim 51, wherein said TCP state machine supports the TCP protection against wrapped sequence numbers (PAWS) using dedicated and optimized hardwired logic

56. The process of claim 51, wherein said TCP state machine supports TCP keep-alive timers using dedicated and optimized hardwired logic

57. The process of claim 51, wherein said TCP state machine supports TCP slow start algorithm.

58. The process of claim 51, wherein said TCP state machine supports TCP fast-retransmission algorithm and fast-recovery algorithm.

59. The process of claim 51, wherein said TCP state machine supports TCP Nagle algorithm using either an internal processor or dedicated hardwired logic.

60. The process of claim 51, wherein said TCP state machine supports TCP selective-acknowledgement (SACK) option.

61. The process of claim 51, wherein said TCP state machine measures packet round-trip times.

62. The process of claim 51, wherein said TCP state machine performs congestion-avoidance algorithms.

63. The process of claim 51, wherein said TCP state machine supports TCP scaling-window using dedicated and optimized hardwired logic.

64. The process of claim 51, wherein said TCP state machine supports maximum-segment size (MSS) discovery using dedicated and optimized hardwired logic.

65. The process of claim 51, wherein said TCP state machine supports time-wait assassination using dedicated and optimized hardwired logic.

66. The process of claim 51, wherein said TCP state machine supports port forwarding using dedicated and optimized hardwired logic.

67. The process of claim 48, further comprising the step of:

providing an IP router module;

wherein said IP router module performs any of;

default IP routing capabilities including hardware to network address translation;

routing for multiple host IP addresses;

routing for host-specific and network-specific routes;

dynamic update of routing information after receiving an ICMP redirect packet message;

routing with IP broadcast addresses, including, but not limited to;

limited broadcasts, subnet-directed broadcasts, and network-directed broadcasts;

routing with loopback IP addresses; and

routing with IP multicast addresses.

68. The process of claim 48, wherein said protocol state machines include an IP protocol state machine, and wherein said IP state machine processes, generates, and responds to IP network packets.

69. The process of claim 68, wherein said IP module comprises dedicated and optimized hardwired logic for defragmenting IP network packets.

70. The process of claim 48, wherein said protocol modules include an ICMP module comprising dedicated and optimized hardwired logic for processing, generating, and responding to ICMP or IGMP network messages.

71. The process of claim 48, wherein said protocol modules include an ICMP module consisting of optimized hardwired logic that can be programmed to hand certain ICMP or IGMP functions to an internal or external processor.

72. The process of claim 48, further comprising:

an IP identification generator module that uses dedicated optimized hardwired logic to generate an identification field for IP packets that has a true random distribution and prevents attempts to predict future values of the identification field.

73. The process of claim 48, wherein said protocol state machines include a virtual socket state machine that allows the use of a virtual number of network connections.

74. The process of claim 48, wherein said protocol state machines include a receive-state handler state machine, wherein said receive-state handler state machine responds to IP network packets in an automated fashion, including any of:

the generation of reset (RST) packets;

the generation of synchronize with acknowledgement packets (SYN/ACK);

the generation of acknowledgement packets (ACK);

the generation of synchronization packets (SYN);

the generation of finish packets (FIN);

the generation of finish/acknowledgement packets (FIN/ACK); and

the generation of reset/acknowledgement packets (RST/ACK).

75. The process of claim 48, wherein said protocol state machines include an ARP protocol state machine, and wherein said ARP state machine responds to network ARP requests by generating network ARP replies.

76. The process of claim 75, wherein said ARP module generates any of:

ARP requests in combination with a hardware ARP address cache;

ARP requests for multiple IP addresses;

unicast ARP requests; and

gratuitous ARP requests.

77. The process of claim 75, wherein said ARP state machine is programmed to hand certain ARP functions to an internal or external processor.

78. The process of claim 75, wherein said ARP state machine is programmed with varying priorities.

79. The process of claim 75, further comprising the step of:

providing a cache for ARP addresses constructed using optimized hardwired logic;

wherein said ARP cache uses a dynamically sized table controlled by dedicated hardware;

wherein said ARP cache supports the ability to act as an ARP proxy; and

wherein said ARP cache uses dedicated hardwired logic to control the expiration time of ARP cache entries.

80. The process of claim 48, wherein said protocol state machines include an RARP protocol state machine, and wherein said RARP state machine can request or supply an IP address.

81. The process of claim 80, wherein said RARP state machine is programmed to hand certain RARP functions to an internal or external processor.

82. The process of claim 48, further comprising the step of:

providing a memory structure that permits hardwired virtual memory management;

wherein said memory structure comprises;

a set of different sized control blocks each optimized for their purpose; and

a mechanism to link control blocks using pointers stored in each control block.

83. The process of claim 82, wherein said hardwired virtual memory management allocates control blocks, updates control blocks, and deallocates control blocks.

84. The process of claim 48, further comprising the step of:

providing a priority queue that schedules packets for transmission according to programmable priority.

85. The process of claim 48, further comprising the step of:

providing a sequencer that calculates and assigns priorities for network packets to be processed.

86. The process of claim 48, further comprising the step of:

providing a memory architecture that stores network information on the state of each network connection in such a manner that it protects against network denial of service attacks.

87. The process of claim 48, wherein said network stack processes, generates and receives TCP and IP packets, and wherein said network stack is programmed to hand certain IP or TCP packet processing functions to an internal or external processor.

88. The process of claim 48, wherein said network stack processes, generates and receives IP packets that encapsulate upper-level protocols such as iSCSI or RDMA.

89. The process of claim 48, further comprising the step of:

providing a virtual memory manager implemented in hardwired logic.

90. The process of claim 89, wherein said virtual memory manager allows the use of a virtual number of network connections, and wherein said virtual number of network connections is limited only by the amount of internal or external memory available.

91. The process of claim 89, wherein said virtual memory manager uses a hardwired locking mechanism to prevent interference between memory locations.

92. The process of claim 89, wherein said virtual memory manager uses a chain of memory structures to store network connection information in memory.

93. The process of claim 89, wherein said virtual memory manager uses dedicated hardwired circuits to search, update, insert, and delete entries in a linked list or chain of memory structures.

94. The process of claim 89, wherein said virtual memory manager uses several different types of control blocks to store network connection information, depending on the state of the network connection.