Twin p-well CMOS imager
First Claim
Patent Images
1. An imaging device comprising:
- a photosensitive area within a substrate for accumulating photo-generated charge in said area;
a readout circuit comprising at least an output transistor formed in said substrate; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage.
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Abstract
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.
52 Citations
133 Claims
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1. An imaging device comprising:
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a photosensitive area within a substrate for accumulating photo-generated charge in said area;
a readout circuit comprising at least an output transistor formed in said substrate; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An imaging device comprising:
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a photosensitive device overlying a substrate for causing accumulation of the photo-generated charge in an underlying portion of said substrate;
a readout circuit comprising at least an output transistor formed in said substrate;
a reset transistor for resetting said node to a predetermined voltage;
a row select transistor; and
at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An imaging system for generating an output signal based on an image focused on the imaging system, the imaging system comprising:
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a plurality of pixel sensors arranged into an array of rows and columns, each pixel sensor being operable to generate a voltage at a diffusion node in a substrate corresponding to detected light intensity by the sensor;
at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage;
a row select device to effectively operate said pixel sensors;
a row decoder having a plurality of control lines connected to the sensor array, each control line being connected to the pixel sensors in a respective row, wherein the row decoder is operable to activate the pixel sensors in a row by said row select device; and
a plurality of output circuits, each output circuit being connected to the respective pixel sensors in a column, each output circuit being operable to is store voltage signals received from a respective pixel sensor and to provide a pixel sensor output signal. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a readout circuit comprising at least an output transistor formed in said substrate; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
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55. A method for reducing the charge leakage across transistors formed in a substrate of a CMOS imager circuit, said method comprising negatively biasing said substrate with a substrate voltage pump, wherein said substrate voltage pump provides a voltage of from about −
- 2.5 to about 2.5 volts to said substrate.
- View Dependent Claims (80)
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56. An imaging device comprising:
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a substrate;
a photosensitive area within a first conductively doped well formed in said substrate for accumulating photo-generated charge in said area; and
a readout circuit formed in a second conductively doped well. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83)
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84. An imaging device including a semiconductor integrated circuit substrate, said imaging device comprising:
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a photosensitive device formed in a first p-well in said substrate for accumulating photo-generated charge in an underlying portion of said substrate;
a readout circuit formed in a second conductively doped well;
a reset transistor formed in said first p-well in said substrate for resetting said node; and
a row select transistor formed in said first p-well in said substrate. - View Dependent Claims (85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108)
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109. An imaging system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a photosensitive area within a first p-well formed in a substrate for accumulating photo-generated charge in said area; and
a readout circuit formed in a second conductively doped well. - View Dependent Claims (110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133)
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Specification