Semiconductor memory device

• US 20030169622A1
• Filed: 12/23/2002
• Published: 09/11/2003
• Est. Priority Date: 03/06/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kato, Hiroshi, Ooishi, Tsukasa, Ohtani, Jun
• Granted Patent: US 6,807,101 B2
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure

Abstract

A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

Claims

1. A non-volatile semiconductor memory device comprising:

a plurality of non-volatile memory cells each storing data in a non-volatile manner and each including a memory cell transistor having a threshold voltage changed in accordance with storage data;

detection circuitry for detecting and storing a change in threshold voltage characteristic of the plurality of non-volatile memory cells;

read circuitry for reading stored data in a selected memory cell of said plurality of non-volatile memory cells, said read circuitry reading the stored data in said selected memory cell in accordance with comparison of a read current corresponding to a current flowing in said selected memory cell with a reference current; and

reference current control circuitry for setting a quantity of said reference current in accordance with a result of detection by said detection circuitry.

2. The non-volatile semiconductor memory device according to claim 1, wherein

said reference current control circuitry changes said reference current, in accordance with a result of detection by said detection circuit, such that an influence on said read current exerted by the change in threshold voltage characteristic of said selected memory cell is cancelled.

3. The non-volatile semiconductor memory device according to claim 1, wherein

each memory cell transistor has the threshold voltage changed in accordance with an associated change in threshold voltage characteristic, and

said reference current control circuitry, according to the result of detection by said detection circuitry, increases a magnitude of said reference current when said read current increases in accordance with the change in threshold voltage characteristic of said selected memory cell.

4. The non-volatile semiconductor memory device according to claim 1, wherein

each memory cell transistor has the threshold voltage changed in accordance with an associated change in threshold voltage characteristic, and

said reference current control circuitry, according to the result of detection by the detection circuitry, decreases a magnitude of said reference current said read current decreases in accordance with the change in threshold voltage characteristic of said selected memory cell.

5. The non-volatile semiconductor memory device according to claim 1, wherein

said detection circuitry includes:

an address storage circuit for storing an address of a memory cell changing in threshold voltage characteristic; and

a comparison circuit for comparing an applied address designating said selected memory cell with a stored address in said address storage circuit and outputting a signal indicating a result of comparison, and

said reference current control circuitry sets the quantity of said reference circuit in accordance with said result of comparison.

6. The non-volatile semiconductor memory device according to claim 5, wherein

said address storage circuit stores an address indicating a location of a memory cell and information indicating a direction of a change in threshold voltage of a memory cell of a corresponding address due to the associated change in threshold voltage characteristic.

7. The non-volatile semiconductor memory device according to claim 5, wherein

said address storage circuit includes:

a first address storage circuit for storing an address of a memory cell having a threshold voltage increased in accordance with the associated change in threshold voltage characteristic; and

a second address storage circuit for storing an address of a memory cell having a threshold voltage decreased in accordance with an associated change in threshold voltage characteristic.

8. A semiconductor memory device comprising:

a plurality of memory cells arranged in rows and columns;

a plurality of bit lines, provided corresponding to the memory cell columns, each connecting to the memory cells on a corresponding column connected;

a plurality of sense amplifiers, electrically coupled commonly to a bit line connecting to an addressed memory cell of said plurality of memory cells, each for amplifying data of said addressed memory cell appearing on said bit line when activated; and

sense control circuitry for controlling operations of said plurality of sense amplifiers in different ways from each other.

9. The semiconductor memory device according to claim 8, wherein

each of said plurality of sense amplifiers compares a read current corresponding to a current flowing the bit line connecting to the addressed memory cell with reference data on a reference data line and outputs a signal indicating a result of comparison.

10. The semiconductor memory device according to claim 9, wherein

said reference data line transmits a reference current as said reference data, and

each sense amplifier compares a read current corresponding to the current flowing through the bit line connecting to the addressed memory cell with the reference current, and outputs a signal indicating a result of comparison.

11. The semiconductor memory device according to claim 8, wherein

said sense control circuitry activates said plurality of sense amplifies such that sensing margin for the data of the addressed memory cell is different for a different sense amplifier.

12. The semiconductor memory device according to claim 8, further comprising

detection circuitry for detecting a sense margin failure for the stored data of said addressed memory cell in accordance with output signals of said plurality of sense amplifiers.

13. The semiconductor memory device according to claim 8, further comprising

internal read circuitry for generating internal read data corresponding to the stored data of said addressed memory cell in accordance with an output signal of a prescribed sense amplifier of said plurality of sense amplifiers.

14. A semiconductor memory device comprising:

a plurality of memory cells;

reference circuitry for generating and outputting reference data having a condition thereof changeable;

internal read circuitry for comparing data read from a selected memory cell of said plurality of memory cells with said reference data and reading the data in said selected memory cell on the basis of a result of comparison; and

reference data control circuitry for selectively changing, in a specific operation mode, the condition set for the reference data outputted by said reference circuitry in accordance with an address of said selected memory cell.

15. The semiconductor memory device according to claim 14, wherein

each of said plurality of memory cells includes a memory transistor having an charge accumulating region accumulating a charge and having a threshold voltage changed in accordance with the charge accumulated in said charge accumulating region, and

said reference data control circuitry changes the set condition for said reference dada in a verify operation mode for detecting whether charges corresponding to stored data are accumulated in said charge accumulating region of said selected memory cell.

16. The semiconductor memory device according to claim 15, wherein

said verify operation mode is an operating mode of detecting whether said selected memory cell is set to a first state where a charge is extracted from said charge accumulating region,

said reference data is a current flow, and

said reference data control circuitry changes a quantity of the current flow as said reference data on the basis of a threshold voltage of a memory cell in said first state.

17. The semiconductor memory device according to claim 15, wherein

said verify operation mode is an operating mode of detecting whether said selected memory cell is set to a first state where a charge is injected into said charge accumulating region,

said reference data is a current flow, and

said reference data control circuitry changes a quantity of the current flow as said reference data on the basis of a threshold voltage of a memory cell in said first state.

18. The semiconductor memory device according to claim 14, further comprising:

an address storage circuit for storing an address; and

a determination circuit for determining whether an address stored in said address storage circuit is designated in a read mode for reading the data in said selected memory cell, wherein

said reference data control circuitry changes the condition set for said reference data when said determination circuit determines that a stored address is designated.

19. The semiconductor memory device according to claim 18, wherein

said internal read circuitry includes a circuit for comparing a current corresponding to the data in said selected memory cell with a reference current corresponding to said reference data, and

said reference data control circuitry changes a magnitude of said reference current.