Semiconductor device having a bond pad and method therefor

• US 20030173667A1
• Filed: 03/13/2002
• Published: 09/18/2003
• Est. Priority Date: 03/13/2002
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Harper, Peter R., Leal, George R., Yong, Lois E., Tran, Tu Anh, Metz, Jeffrey W., Dinh, Dieu Van
• Granted Patent: US 6,844,631 B2
• Time in Patent Office: Days
• US Class Current: 257/748
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Claims

1. An integrated circuit comprising:

a substrate having active circuitry and a perimeter;

a plurality of layers of interconnect over the substrate;

a final layer of interconnect over the plurality of layers of interconnect having a final layer pad and a plurality of interconnect lines;

a layer of passivation over the final layer of interconnect having an opening over the final layer pad; and

a bond pad over and electrically contacting the final layer pad having a first region and a second region, wherein the first region is between the second region and the perimeter, the first and second regions are substantially non-overlapping and contiguous, and the first region performs a function of one of a probe region and a wire bond region and the second region performs the function of one of probe region and wire bond region not performed by the first region.

2. The integrated circuit of claim 1, wherein the opening has a first width and the bond pad extends over the surface of the passivation past the opening in at least one direction by an amount greater than the first width.

3. The integrated circuit structure of claim 1 wherein the opening is filled with tantalum and aluminum.

4. The integrated circuit of claim 1, wherein the final layer pad is copper.

5. The integrated circuit of claim 1 wherein the bond pad comprises a layer of barrier conductor on the layer of passivation and in the opening and a layer of pad metal over the barrier conductor.

6. The integrated circuit of claim 5, wherein the barrier conductor comprises tantalum and the pad metal layer comprises aluminum

7. The integrated circuit of claim 5, wherein the barrier conductor is tantalum nitride.

8. The integrated circuit of claim 5, wherein the barrier conductor is selected from one or more of tantalum, titanium nitride, tantalum nitride, and titanium.

9. The integrated circuit of claim 5, wherein the barrier conductor comprises means for providing electrical conduction and adhesion between the final layer pad and the bond pad.

10. The integrated circuit of claim 5, wherein the pad metal is gold.

11. An integrated circuit, comprising:

a substrate having active circuitry;

a plurality of layers of interconnect over the substrate;

a final layer of interconnect over the plurality of layers of interconnect having a plurality of final layer pads around a perimeter of the substrate and having a plurality of interconnect lines;

a layer of passivation over the final layer of interconnect having a plurality openings, wherein each of the plurality of openings corresponds to a final layer pad of the plurality of final layer pads and each of the plurality of openings is over the final layer pad to which it corresponds; and

a plurality bond pads, wherein each bond pad of the plurality of bond pads corresponds to an opening of the plurality of openings, each bond pad is over the opening to which it corresponds, each bond pad has a first region and a second region, wherein the first region of each bond pad is closer to the perimeter of the substrate than the second region of each bond pad, and wherein first regions of adjacent bond pads alternate between probe regions and wire bond regions.

12. The integrated circuit 11, wherein the first region and second region of each bond pad is one of the probe region and the wire bond region.

13. The integrated circuit of claim 12, wherein a distance between centers of probe regions of the adjacent bond pads is greater than between centers of the adjacent pads.

14. The integrated circuit of claim 12, wherein second regions of the adjacent bond pads alternate between wire bond regions and probe regions.

15. The integrated circuit of claim 14, wherein each of the plurality of openings has a first width and each of the plurality of bond pads extend over the surface of the passivation past the opening to which it corresponds in at least one direction by an amount greater than the first width.

16. The integrated circuit of claim 15, wherein each of the plurality of bond pads extends over the active circuitry.

17. An integrated circuit, comprising:

a substrate having active circuitry and a perimeter;

a first plurality of interconnect layers over the substrate;

a plurality of final layer pads over the first plurality of interconnect layers;

a passivation layer having a plurality of openings corresponding to the final layer pads; and

a plurality of bond pads, coupled to the final layer pads through the openings, having first portions over the openings and second portions over the passivation layer, wherein the second portion is greater in area than the first portion.

18. The integrated circuit of claim 17, wherein the plurality of bond pads each have first and second regions, wherein one of the first and second regions is for receiving a probe and the other of the first and second regions is for receiving a wire bond, wherein the first and second regions are substantially non-overlapping.

19. The integrated circuit of claim 18, wherein the first regions are nearer the perimeter of the substrate than the second regions, and a first bond pad and a second bond pad of the plurality of bond pads are adjacent to each other, and the first region of the first bond pad and the second region of the second bond pad are for receiving the probe.

20. The integrated circuit of claim 17, wherein the plurality of bond pads extend over the active circuitry and the second portion is significantly greater than the first portion.

21. The integrated circuit of claim 19, wherein the first regions of the first and second bond pads are mostly in the second portions.

22. A method of forming an integrated circuit comprising:

providing a substrate having active circuitry;

forming a plurality of layers of interconnect over the substrate;

forming a final layer of interconnect over the plurality of layers of interconnect having a plurality of final layer pads around a perimeter of the substrate and having a plurality of interconnect lines;

forming a layer of passivation over the final layer of interconnect having a plurality openings, wherein each of the plurality of openings corresponds to a final layer pad of the plurality of final layer pads and each of the plurality of openings is over the final layer pad to which it corresponds; and

forming a plurality of bond pads coupled to the final layer pads through the openings, wherein each bond pad of the plurality of bond pads;

corresponds to an opening of the plurality of openings;

has a first portion over the opening to which it corresponds and a second portion over the passivation layer, wherein the second portion is greater in area than the first portion; and

has a first region and a second region that are substantially non-overlapping, wherein the first region of each bond pad is closer to the perimeter of the substrate than the second region of each bond pad, and wherein first regions of adjacent bond pads alternate between probe regions and wire bond regions.

23. A method of forming an integrated circuit having:

a substrate having active circuitry and a perimeter;

a plurality of layers of interconnect over the substrate;

a final layer of interconnect over the plurality of layers of interconnect having a first final layer pad, a second final layer pad, and a plurality of interconnect lines;

a layer of passivation over the final layer of interconnect having a first opening over the first final layer pad and a second opening over the second final layer pad;

a first bond pad over and electrically contacting the first final layer pad having a first region and a second region, wherein the first region is closer to the perimeter than the second region, and the first and second region are substantially non-overlapping;

a second bond pad over and electrically contacting the second final layer pad having a first region and a second region, wherein the first region is closer to the perimeter than the second region, and the first and second region are substantially non-overlapping;

the method comprising;

applying a first test probe to the first region of the first bond pad;

applying a second test probe to the second region of the second bond pad;

forming a wire bond on the second region of the first bond pad; and

forming a wire bond on the first region of the second bond pad.

24. An integrated circuit, comprising:

a substrate having active circuitry and a perimeter;

a plurality of interconnect layers formed over the substrate, the plurality of interconnect layers having a final interconnect layer;

a plurality of wire bond pads formed over the final interconnect layer, wherein each of the plurality of wire bond pads having a first region and a second region, the first region being used only as a probe region, and the second region being used only as a wire bond region, and wherein the plurality of interconnect layers and active circuitry underlying the plurality of wire bond pads; and

a passivation layer formed over the final interconnect layer and having a plurality of openings, each of the plurality of openings corresponding to one of the plurality of wire bond pads.

25. The integrated circuit of claim 24, wherein the plurality of interconnect layers and the plurality of wire bond pads comprise copper.

26. The integrated circuit of claim 25, further comprising a plurality of aluminum pads, each of the plurality of aluminum pads formed on one of the plurality of wire bond pads.

27. The integrated circuit claim 24, wherein the plurality of wire bond pads are formed in a line along the perimeter, and wherein the second region of each bond pad is closer to the perimeter of the substrate than the first region of each bond pad.

28. The integrated circuit of claim 24, wherein the plurality of wire bond pads are formed in a line along the perimeter, and wherein second regions of adjacent bond pads are substantially an equal distance from the perimeter, and the first region of adjacent wire bond pads alternate from a side of the second region relatively closer to the perimeter to another side of the second region relatively farther from the perimeter.

29. The integrated circuit of claim 24, wherein the plurality of wire bond pads are formed in a line along the perimeter, and wherein the first regions of odd numbered wire bond pads of the plurality of wire bond pads are located a first distance from the perimeter and the first regions of even numbered wire bond pads of the plurality of wire bond pads are located a second distance from the perimeter, the first distance being farther from the perimeter than the second distance.

30. The integrated circuit of claim 29, wherein second regions of the odd numbered wire bond pads are located the second distance from the perimeter and second regions of the even numbered wire bond pads are located the first distance from the perimeter.

31. The integrated circuit of claim 24, wherein the plurality of wire bond pads are formed in a line along the perimeter, and wherein the first and second regions of each of the plurality of wire bond pads are formed substantially an equal distance from the perimeter.