Image display circuitry and mobile electronic device

• US 20030174138A1
• Filed: 02/13/2003
• Published: 09/18/2003
• Est. Priority Date: 02/13/2002
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Shibayama, Hiroaki
• Application Number:
  US10/365,518
• Publication Number:
  US 20030174138A1
• Time in Patent Office: Days
• US Class Current: 345/545
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence

Abstract

An image display circuitry comprises frame buffers 32-34 for storing image data DTAW, DTRW and logical combining data DTCW respectively, and a combining circuit 46. Data buses and address buses of the frame buffers 32 and 34 are time-sharingly controllable from an MPU independently of those of the frame buffer 33. Each frame of the image data DTRW is synchronized with a vertical synchronizing signal, and stored to the frame buffer 33. Each frame of the image data DTAW and the logical combining data DTCW is separately and independently stored to the frame buffers 32 and 34 by the MPU within a storage period of a corresponding frame of the image data DTRW. The combining circuit 46 combines image data DTAR and DTBR pixel by pixel on the basis of logical combining data DTCR within a specified period during a vertical retrace period.

Claims

1. An image display circuitry, comprising:

a first frame buffer for storing first image data;

a second frame buffer for storing second image data supplied from a camera;

a third frame buffer for storing logical combining data to be used for combining said first and second image data pixel by pixel; and

a combining circuit for combining said first and second image data by use of said logical combining data;

wherein;

a data bus and an address bus, each of which is connected to said first and third frame buffers, are separate and independent of a data bus and an address bus which are connected to said second frame buffer;

said data bus and said address bus, each of which is connected to said first and third frame buffers, are time-sharingly controllable from outside independently of said data bus and said address bus which are connected to said second frame buffer; and

said first and second image data and said logical combining data are time-sharingly stored and combined in said combining circuit, for one frame within one period of a vertical synchronizing signal for said second image data.

2. An image display circuitry according to claim 1, wherein:

each frame of said second image data is synchronized with a vertical synchronizing signal for said second image data, and stored to said second frame buffer;

each frame of said first image data and said logical combining data is separately and independently stored from outside to said respective first and third frame buffers within a period of storing a corresponding frame of said second image data to said second frame buffer; and

said combining circuit combines, pixel by pixel, said first and second image data read from said respective first and second frame buffers by use of said logical combining data read from said third frame buffer within a specified period during a vertical retrace period of said vertical synchronizing signal.

3. An image display circuitry according to claim 1, wherein said combining circuit combines one of said first and second image data with the other as a telop picture of a static or moving image.

4. An image display circuitry according to claim 1, wherein said combining circuit combines one of said first and second image data with the other as a wipe picture that wipes a picture from one corner and immediately displays a next picture.

5. An image display circuitry according to claim 1, further comprising:

a color increasing circuit for increasing a color of said first image data read from said first frame buffer to a color displayable on a display, and then supplying its processed result to said combining circuit; and

a color decreasing circuit for decreasing a color of said second image data read from said second frame buffer to a color displayable on said display, and then supplying its processed result to said combining circuit.

6. An image display circuitry according to claim 1, further comprising:

a conversion circuit for converting said second image data supplied from said camera into third image data of a form displayable on a display; and

a first reduction circuit for reducing a pixel number of said third image data to a display pixel number of said display.

7. An image display circuitry according to claim 6, wherein said first reduction circuit performs smart processing in reducing said third image data in a line, wherein values of adjacent image data are computed, and its computed result is divided into two.

8. An image display circuitry according to claim 1, further comprising:

a second reduction circuit for reducing said second image data supplied from said camera to fourth image data compressible into image data of JPEG form; and

a compression circuit for compressing said fourth image data into image data of said JPEG form, and then storing it to said first to third frame buffers that are treated as a single whole frame buffer.

9. An image display circuitry according to claim 8, wherein said second reduction circuit performs smart processing in reducing said fourth image data in a line, wherein values of adjacent image data are computed, and its computed result is divided into two.

10. An image display circuitry according to claim 1, further comprising a filtering circuit for performing any one of the following filterings on said second image data supplied from said camera:

sepia, brightness adjustment, grey scale, tone binarization, edge enhancement, edge extraction.

11. A mobile electronic device, comprising:

an image display circuitry comprising;

a first frame buffer for storing first image data;

a second frame buffer for storing second image data;

a third frame buffer for storing logical combining data to be used for combining said first and second image data pixel by pixel; and

a combining circuit for combining said first and second image data by use of said logical combining data;

a camera for supplying said second image data to said image display circuitry; and

a display for displaying image data supplied from said image display circuitry, wherein;

a data bus and an address bus, each of which is connected to said first and third frame buffers, are separate and independent of a data bus and an address bus which are connected to said second frame buffer;

said data bus and said address bus, each of which is connected to said first and third frame buffers, are time-sharingly controllable from outside independently of said data bus and said address bus which are connected to said second frame buffer; and

said first and second image data and said logical combining data are time-sharingly stored and combined in said combining circuit, for one frame within one period of a vertical synchronizing signal for said second image data.

12. A mobile electronic device according to claim 11, wherein said first image data is any of:

static image data;

moving image data;

illustration data;

animation data;

static/moving image data for a frame for decorating a periphery of said second image data;

a waiting picture displayed while waiting for incoming data without any operation by a user although with the device powered on;

a screen saving picture displayed for preventing burning in after said waiting picture is displayed for a specified time;

a game picture.

13. A mobile electronic device according to claim 12, wherein said screen saving picture is an animation pattern, a pattern with which characters that are changed according to season move freely around in a display screen.

14. A mobile electronic device according to claim 12, wherein said game picture is a character raising game for raising selected characters by a user feeding or cherishing them.

15. A mobile electronic device, comprising:

a camera for generating image data to be displayed;

a circuit for processing said image data supplied from said camera to provide processed image data, and generating an address signal to determine a storage address of said processed image data;

a frame buffer for storing said processed image data at said storage address;

a data bus for transferring said processed image data from said processing circuit to said frame buffer; and

a display for displaying an image by use of said processed image data read from said frame buffer.

16. A mobile electronic device according to claim 15, wherein said frame buffer comprises:

a first storage region for storing image data supplied from an MPU;

a second storage region for storing said processed image data; and

a third storage region for storing data to be used for combining said image data read from said first and second storage regions;

wherein

said display displays an image obtained from combining said image data read from said first and second storage regions by use of said data read from said third storage region.

17. A mobile electronic device according to claim 15, further comprising a data bus for transferring said image data from said MPU to said first storage region of said frame buffer.

18. A mobile electronic device according to claim 15, wherein said processing circuit comprises:

a filtering circuit for filtering said image data supplied from said camera;

a first reduction circuit for reducing said image data filtered by said filtering circuit to image data compressible into JPEG form; and

a compression circuit for compressing said image data reduced by said first reduction circuit into image data of said JPEG form.

19. A mobile electronic device according to claim 15, wherein said processing circuit comprises:

a filtering circuit for filtering said image data supplied from said camera;

a conversion circuit for converting said image data filtered by said filtering circuit into image data of a form displayable on said display; and

a second reduction circuit for reducing a pixel number of said image data converted by said conversion circuit to a display pixel number of said display.

20. A mobile electronic device according to claim 15, wherein said processing circuit comprises:

a filtering circuit for filtering said image data supplied from said camera;

a first reduction circuit for reducing said image data filtered by said filtering circuit to image data compressible into JPEG form;

a compression circuit for compressing said image data reduced by said first reduction circuit into image data of said JPEG form;

a conversion circuit for converting said image data filtered by said filtering circuit into image data of a form displayable on said display; and

a second reduction circuit for reducing a pixel number of said image data converted by said conversion circuit to a display pixel number of said display.